OpenASIP 2.2
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AlteraOnchipRomGenerator.cc
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1/*
2 Copyright (c) 2002-2010 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file AlteraOnchipRomGenerator.cc
26 *
27 * Implementation of AlteraOnchipRomGenerator class.
28 *
29 * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
30 * @note rating: red
31 */
32
33#include <iostream>
34#include <vector>
36#include "PlatformIntegrator.hh"
37#include "HDLPort.hh"
38using std::endl;
40
42 "altera_onchip_rom_comp.vhd";
43
45 int memMauWidth,
46 int widthInMaus,
47 int addrWidth,
48 TCEString initFile,
49 const PlatformIntegrator* integrator,
50 std::ostream& warningStream,
51 std::ostream& errorStream):
52 AlteraMemGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
53 integrator, warningStream, errorStream) {
54
55 bool noInvert = false;
56 bool inverted = true;
57
58 addPort("clk",
59 new HDLPort("clock", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
60 addPort("imem_addr",
61 new HDLPort("address", "IMEMADDRWIDTH", ProGe::BIT_VECTOR,
62 ProGe::IN, noInvert));
63 addPort("imem_en_x",
64 new HDLPort("clken", "1", ProGe::BIT, ProGe::IN, inverted, 1));
65 addPort("imem_data",
66 new HDLPort("q", "IMEMWIDTHINMAUS*IMEMMAUWIDTH",
67 ProGe::BIT_VECTOR, ProGe::OUT, noInvert));
68
69 // these signals are not driven by the imem component, connect to zero
70 HDLPort* busyToGnd =
71 new HDLPort("wait", "1", ProGe::BIT, ProGe::OUT, noInvert, 1);
73 addPort("busy", busyToGnd);
74}
75
76
79
80bool
84
85
86std::vector<TCEString>
91
92void
94 const ProGe::NetlistBlock& ttaCore,
95 ProGe::NetlistBlock& integratorBlock,
96 int memIndex,
97 int coreId) {
98
99 // Add generics as string constants!
100 TCEString addrwGeneric = "IMEMADDRWIDTH";
101 TCEString datawGeneric = "IMEMWIDTHINMAUS*IMEMMAUWIDTH";
102 addGenerics(integratorBlock, addrwGeneric, datawGeneric, memIndex);
103
104 MemoryGenerator::addMemory(ttaCore, integratorBlock, memIndex, coreId);
105}
106
109
110 return ttaCoreName() + "_altera_onchip_rom_comp";
111}
112
113
115AlteraOnchipRomGenerator::instanceName(int coreId, int memIndex) const {
116
117 TCEString iname("onchip_imem_");
118 return iname << memoryIndexString(coreId, memIndex);
119}
std::vector< TCEString > instantiateAlteraTemplate(const TCEString &templateFile, const TCEString &outputPath) const
virtual void addGenerics(ProGe::NetlistBlock &topBlock, const TCEString &addrWidth, const TCEString &dataWidth, int memIndex)
virtual void addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
virtual bool generatesComponentHdlFile() const
static const TCEString COMPONENT_FILE
virtual std::vector< TCEString > generateComponentFile(TCEString outputPath)
virtual TCEString moduleName() const
virtual TCEString instanceName(int coreId, int memIndex) const
AlteraOnchipRomGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
void setToStatic(ProGe::StaticSignal value)
Definition HDLPort.cc:145
TCEString memoryIndexString(int coreId, int memIndex) const
void addPort(const TCEString &name, HDLPort *port)
virtual void addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
TCEString ttaCoreName() const
@ GND
All port signals set to low.
@ BIT
One bit.
Definition ProGeTypes.hh:47
@ BIT_VECTOR
Several bits.
Definition ProGeTypes.hh:48
@ OUT
Output port.
Definition ProGeTypes.hh:54
@ IN
Input port.
Definition ProGeTypes.hh:53