OpenASIP  2.0
Stratix2DSPBoardIntegrator.cc
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1 /*
2  Copyright (c) 2002-2010 Tampere University.
3 
4  This file is part of TTA-Based Codesign Environment (TCE).
5 
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24 /**
25  * @file Stratix2DSPBoardIntegrator.cc
26  *
27  * Implementation of Stratix2DSPBoardIntegrator class.
28  *
29  * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
30  * @note rating: red
31  */
32 
33 #include <iostream>
34 #include <map>
35 #include <vector>
36 #include "Exception.hh"
37 #include "Stratix2DSPBoardIntegrator.hh"
38 #include "Stratix2SramGenerator.hh"
39 #include "Netlist.hh"
40 #include "NetlistBlock.hh"
41 #include "VirtualNetlistBlock.hh"
42 #include "NetlistPort.hh"
43 #include "FileSystem.hh"
44 #include "Machine.hh"
45 using std::vector;
46 using std::endl;
47 using ProGe::Netlist;
48 using ProGe::NetlistBlock;
49 using ProGe::VirtualNetlistBlock;
50 using ProGe::NetlistPort;
51 using PlatInt::SignalMapping;
52 using PlatInt::SignalMappingList;
53 
54 const TCEString Stratix2DSPBoardIntegrator::DEVICE_FAMILY_ = "Stratix II";
55 const TCEString Stratix2DSPBoardIntegrator::DEVICE_NAME_ =
56  "EP2S180F1020C3";
57 const TCEString Stratix2DSPBoardIntegrator::DEVICE_PACKAGE_ = "F1020";
58 const TCEString Stratix2DSPBoardIntegrator::DEVICE_SPEED_CLASS_ = "3";
59 const TCEString Stratix2DSPBoardIntegrator::PIN_TAG_ = "STRATIXII";
60 const int Stratix2DSPBoardIntegrator::DEFAULT_FREQ_ = 100;
61 
62 
63 Stratix2DSPBoardIntegrator::Stratix2DSPBoardIntegrator():
64  AlteraIntegrator(), quartusGen_(NULL) {
65 
66 }
67 
68 Stratix2DSPBoardIntegrator::Stratix2DSPBoardIntegrator(
69  const TTAMachine::Machine* machine,
70  const IDF::MachineImplementation* idf,
71  ProGe::HDL hdl,
72  TCEString progeOutputDir,
73  TCEString coreEntityName,
74  TCEString outputDir,
75  TCEString programName,
76  int targetClockFreq,
77  std::ostream& warningStream,
78  std::ostream& errorStream,
79  const MemInfo& imem,
80  MemType dmemType):
81  AlteraIntegrator(machine, idf, hdl, progeOutputDir, coreEntityName,
82  outputDir, programName, targetClockFreq, warningStream,
83  errorStream, imem, dmemType),
84  quartusGen_(new QuartusProjectGenerator(coreEntityName, this)),
85  dmemGen_(NULL) {
86  setDeviceName(DEVICE_NAME_);
87 }
88 
89 
90 Stratix2DSPBoardIntegrator::~Stratix2DSPBoardIntegrator() {
91 
92  for (PlatInt::PinMap::iterator iter = stratix2Pins_.begin();
93  iter != stratix2Pins_.end(); iter++) {
94  if (iter->second != NULL) {
95  for (unsigned int i = 0; i < iter->second->size(); i++) {
96  delete iter->second->at(i);
97  }
98  delete iter->second;
99  }
100  }
101  if (quartusGen_ != NULL) {
102  delete quartusGen_;
103  }
104 
105  if (dmemGen_ != NULL) {
106  delete dmemGen_;
107  }
108 }
109 
110 void
111 Stratix2DSPBoardIntegrator::integrateProcessor(
112  const ProGe::NetlistBlock* ttaCore) {
113 
114  generatePinMap();
115 
116  initPlatformNetlist(ttaCore);
117 
118  const NetlistBlock& core = progeBlock();
119  int coreId = -1;
120  if (!integrateCore(core, coreId)) {
121  return;
122  }
123 
124  mapToplevelPorts();
125 
126  writeNewToplevel();
127 
128  addProGeFiles();
129 
130  projectFileGenerator()->writeProjectFiles();
131 }
132 
133 MemoryGenerator&
134 Stratix2DSPBoardIntegrator::dmemInstance(
135  MemInfo dmem, TTAMachine::FunctionUnit& lsuArch,
136  std::vector<std::string> lsuPorts) {
137  if (dmem.type == ONCHIP) {
138  return AlteraIntegrator::dmemInstance(dmem, lsuArch, lsuPorts);
139  } else if (dmem.type == SRAM) {
140  if (dmemGen_ == NULL) {
141  TCEString initFile = programName() + "_" + dmem.asName + ".img";
142  // SRAM component has fixed size, thus use the addr width from hdb
143  int addrw = dmem.portAddrw;
144  dmemGen_ =
145  new Stratix2SramGenerator(
146  dmem.mauWidth, dmem.widthInMaus, addrw, initFile,
147  this, warningStream(), errorStream());
148  warningStream() << "Warning: Data memory is not initialized "
149  << "during FPGA programming." << endl;
150  dmemGen_->addLsu(lsuArch, lsuPorts);
151  }
152  } else {
153  TCEString msg = "Unsupported data memory type";
154  throw InvalidData(__FILE__, __LINE__, "Stratix2DSPBoardIntegrator",
155  msg);
156  }
157  return *dmemGen_;
158 }
159 
160 void
161 Stratix2DSPBoardIntegrator::mapToplevelPorts() {
162  NetlistBlock& tl = *integratorBlock();
163  for (size_t i = 0; i < tl.portCount(); i++) {
164  addSignalMapping(tl.port(i).name());
165  }
166 }
167 
168 void
169 Stratix2DSPBoardIntegrator::addSignalMapping(const TCEString& signal) {
170 
171  if (stratix2Pins_.find(signal) == stratix2Pins_.end()) {
172  warningStream() << "Warning: didn't find mapping for signal name "
173  << signal << endl;
174  return;
175  }
176 
177  SignalMappingList* mappings = stratix2Pins_.find(signal)->second;
178  for (unsigned int i = 0; i < mappings->size(); i++) {
179  quartusGen_->addSignalMapping(*mappings->at(i));
180  }
181 }
182 
183 
184 TCEString
185 Stratix2DSPBoardIntegrator::pinTag() const {
186 
187  return PIN_TAG_;
188 }
189 
190 
191 bool
192 Stratix2DSPBoardIntegrator::chopTaggedSignals() const {
193 
194  return true;
195 }
196 
197 
198 ProjectFileGenerator*
199 Stratix2DSPBoardIntegrator::projectFileGenerator() const {
200 
201  return quartusGen_;
202 }
203 
204 
205 
206 TCEString
207 Stratix2DSPBoardIntegrator::deviceFamily() const {
208 
209  return DEVICE_FAMILY_;
210 }
211 
212 
213 void
214 Stratix2DSPBoardIntegrator::setDeviceFamily(TCEString devFamily) {
215 
216  if (devFamily != DEVICE_FAMILY_) {
217  warningStream()
218  << "Warning: Refusing to change device family!" << endl
219  << "- Original device family: " << DEVICE_FAMILY_ << endl
220  << "- New device family: " << devFamily << endl;
221  }
222 }
223 
224 TCEString
225 Stratix2DSPBoardIntegrator::devicePackage() const {
226 
227  return DEVICE_PACKAGE_;
228 }
229 
230 
231 TCEString
232 Stratix2DSPBoardIntegrator::deviceSpeedClass() const {
233 
234  return DEVICE_SPEED_CLASS_;
235 }
236 
237 int
238 Stratix2DSPBoardIntegrator::targetClockFrequency() const {
239 
240  int freq = DEFAULT_FREQ_;
241 
242  if (PlatformIntegrator::targetClockFrequency() > 0) {
243  freq = PlatformIntegrator::targetClockFrequency();
244  }
245  return freq;
246 }
247 
248 void
249 Stratix2DSPBoardIntegrator::printInfo(std::ostream& stream) const {
250 
251  stream
252  << "Integrator name: Stratix2DSP" << std::endl
253  << "-----------------------------" << std::endl
254  << "Integrates the processor core to Altera Stratix II DSP board "
255  << "with EP2S180F1020C3 device." << std::endl
256  << "Creates project files for QuartusII v8.0 program." << std::endl
257  << "Supported instruction memory types are 'onchip' and 'vhdl_array."
258  << std::endl
259  << "Supported data memory types are 'onchip' and 'sram'." << std::endl
260  << "Default clock frequency is 100 MHz." << std::endl
261  << "Active low reset is connected to CPU RESET button." << std::endl
262  << std::endl;
263 }
264 
265 
266 // keep this in sync with stratixII.hdb
267 void
268 Stratix2DSPBoardIntegrator::generatePinMap() {
269 
270  // clk
271  SignalMappingList* clk = new SignalMappingList;
272  clk->push_back(new SignalMapping("PIN_AM17","clk"));
273  stratix2Pins_["clk"] = clk;
274 
275  // reset to push button CPU_RESET
276  SignalMappingList* rstx = new SignalMappingList;
277  rstx->push_back(new SignalMapping("PIN_AG19","rstx"));
278  stratix2Pins_["rstx"] = rstx;
279 
280  // leds
281  SignalMappingList* ledMapping = new SignalMappingList;
282  ledMapping->push_back(new SignalMapping("PIN_B4","STRATIXII_LED[0]"));
283  ledMapping->push_back(new SignalMapping("PIN_D5","STRATIXII_LED[1]"));
284  ledMapping->push_back(new SignalMapping("PIN_E5","STRATIXII_LED[2]"));
285  ledMapping->push_back(new SignalMapping("PIN_A4","STRATIXII_LED[3]"));
286  ledMapping->push_back(new SignalMapping("PIN_A5","STRATIXII_LED[4]"));
287  ledMapping->push_back(new SignalMapping("PIN_D6","STRATIXII_LED[5]"));
288  ledMapping->push_back(new SignalMapping("PIN_C6","STRATIXII_LED[6]"));
289  ledMapping->push_back(new SignalMapping("PIN_A6","STRATIXII_LED[7]"));
290  stratix2Pins_["STRATIXII_LED"] = ledMapping;
291 
292  // sram data signals
293  SignalMappingList* sramData = new SignalMappingList;
294  sramData->push_back(new SignalMapping("PIN_AD18","STRATIXII_SRAM_DQ[0]"));
295  sramData->push_back(new SignalMapping("PIN_AB18","STRATIXII_SRAM_DQ[1]"));
296  sramData->push_back(new SignalMapping("PIN_AB19","STRATIXII_SRAM_DQ[2]"));
297  sramData->push_back(new SignalMapping("PIN_AC20","STRATIXII_SRAM_DQ[3]"));
298  sramData->push_back(new SignalMapping("PIN_AD20","STRATIXII_SRAM_DQ[4]"));
299  sramData->push_back(new SignalMapping("PIN_AE20","STRATIXII_SRAM_DQ[5]"));
300  sramData->push_back(new SignalMapping("PIN_AB20","STRATIXII_SRAM_DQ[6]"));
301  sramData->push_back(new SignalMapping("PIN_AF20","STRATIXII_SRAM_DQ[7]"));
302  sramData->push_back(new SignalMapping("PIN_AC21","STRATIXII_SRAM_DQ[8]"));
303  sramData->push_back(new SignalMapping("PIN_AD21","STRATIXII_SRAM_DQ[9]"));
304  sramData->push_back(
305  new SignalMapping("PIN_AB21","STRATIXII_SRAM_DQ[10]"));
306  sramData->push_back(
307  new SignalMapping("PIN_AE21","STRATIXII_SRAM_DQ[11]"));
308  sramData->push_back(
309  new SignalMapping("PIN_AG20","STRATIXII_SRAM_DQ[12]"));
310  sramData->push_back(
311  new SignalMapping("PIN_AF21","STRATIXII_SRAM_DQ[13]"));
312  sramData->push_back(
313  new SignalMapping("PIN_AD22","STRATIXII_SRAM_DQ[14]"));
314  sramData->push_back(
315  new SignalMapping("PIN_AF22","STRATIXII_SRAM_DQ[15]"));
316  sramData->push_back(
317  new SignalMapping("PIN_AE22","STRATIXII_SRAM_DQ[16]"));
318  sramData->push_back(
319  new SignalMapping("PIN_AC17","STRATIXII_SRAM_DQ[17]"));
320  sramData->push_back(
321  new SignalMapping("PIN_AE19","STRATIXII_SRAM_DQ[18]"));
322  sramData->push_back(
323  new SignalMapping("PIN_AD19","STRATIXII_SRAM_DQ[19]"));
324  sramData->push_back(
325  new SignalMapping("PIN_AC18","STRATIXII_SRAM_DQ[20]"));
326  sramData->push_back(
327  new SignalMapping("PIN_AB17","STRATIXII_SRAM_DQ[21]"));
328  sramData->push_back(
329  new SignalMapping("PIN_AC19","STRATIXII_SRAM_DQ[22]"));
330  sramData->push_back(
331  new SignalMapping("PIN_AL26","STRATIXII_SRAM_DQ[23]"));
332  sramData->push_back(
333  new SignalMapping("PIN_AL27","STRATIXII_SRAM_DQ[24]"));
334  sramData->push_back(
335  new SignalMapping("PIN_AL28","STRATIXII_SRAM_DQ[25]"));
336  sramData->push_back(
337  new SignalMapping("PIN_AK28","STRATIXII_SRAM_DQ[26]"));
338  sramData->push_back(
339  new SignalMapping("PIN_AK29","STRATIXII_SRAM_DQ[27]"));
340  sramData->push_back(
341  new SignalMapping("PIN_AC13","STRATIXII_SRAM_DQ[28]"));
342  sramData->push_back(
343  new SignalMapping("PIN_AD10","STRATIXII_SRAM_DQ[29]"));
344  sramData->push_back(
345  new SignalMapping("PIN_AC11","STRATIXII_SRAM_DQ[30]"));
346  sramData->push_back(
347  new SignalMapping("PIN_AE11","STRATIXII_SRAM_DQ[31]"));
348  stratix2Pins_["STRATIXII_SRAM_DQ"] = sramData;
349 
350  // sram address signals
351  SignalMappingList* sramAddr = new SignalMappingList;
352  sramAddr->push_back(
353  new SignalMapping("PIN_AM28","STRATIXII_SRAM_ADDR[0]"));
354  sramAddr->push_back(
355  new SignalMapping("PIN_AJ27","STRATIXII_SRAM_ADDR[1]"));
356  sramAddr->push_back(
357  new SignalMapping("PIN_AK27","STRATIXII_SRAM_ADDR[2]"));
358  sramAddr->push_back(
359  new SignalMapping("PIN_AL29","STRATIXII_SRAM_ADDR[3]"));
360  sramAddr->push_back(
361  new SignalMapping("PIN_AM29","STRATIXII_SRAM_ADDR[4]"));
362  sramAddr->push_back(
363  new SignalMapping("PIN_AJ28","STRATIXII_SRAM_ADDR[5]"));
364  sramAddr->push_back(
365  new SignalMapping("PIN_AH28","STRATIXII_SRAM_ADDR[6]"));
366  sramAddr->push_back(
367  new SignalMapping("PIN_AK20","STRATIXII_SRAM_ADDR[7]"));
368  sramAddr->push_back(
369  new SignalMapping("PIN_AJ20","STRATIXII_SRAM_ADDR[8]"));
370  sramAddr->push_back(
371  new SignalMapping("PIN_AL21","STRATIXII_SRAM_ADDR[9]"));
372  sramAddr->push_back(
373  new SignalMapping("PIN_AL22","STRATIXII_SRAM_ADDR[10]"));
374  sramAddr->push_back(
375  new SignalMapping("PIN_AJ22","STRATIXII_SRAM_ADDR[11]"));
376  sramAddr->push_back(
377  new SignalMapping("PIN_AH22","STRATIXII_SRAM_ADDR[12]"));
378  sramAddr->push_back(
379  new SignalMapping("PIN_AL23","STRATIXII_SRAM_ADDR[13]"));
380  sramAddr->push_back(
381  new SignalMapping("PIN_AL24","STRATIXII_SRAM_ADDR[14]"));
382  sramAddr->push_back(
383  new SignalMapping("PIN_AJ25","STRATIXII_SRAM_ADDR[15]"));
384  sramAddr->push_back(
385  new SignalMapping("PIN_AH25","STRATIXII_SRAM_ADDR[16]"));
386  sramAddr->push_back(
387  new SignalMapping("PIN_AL25","STRATIXII_SRAM_ADDR[17]"));
388  stratix2Pins_["STRATIXII_SRAM_ADDR"] = sramAddr;
389 
390  // sram control signals
391  SignalMappingList* sramWe = new SignalMappingList;
392  sramWe->push_back(new SignalMapping("PIN_AH14","STRATIXII_SRAM_WE_N"));
393  stratix2Pins_["STRATIXII_SRAM_WE_N"] = sramWe;
394 
395  SignalMappingList* sramOe = new SignalMappingList;
396  sramOe->push_back(new SignalMapping("PIN_AG14","STRATIXII_SRAM_OE_N"));
397  stratix2Pins_["STRATIXII_SRAM_OE_N"] = sramOe;
398 
399  SignalMappingList* sramCs = new SignalMappingList;
400  sramCs->push_back(new SignalMapping("PIN_AL12","STRATIXII_SRAM_CS_N"));
401  stratix2Pins_["STRATIXII_SRAM_CS_N"] = sramCs;
402 
403  SignalMappingList* sramB0 = new SignalMappingList;
404  SignalMappingList* sramB1 = new SignalMappingList;
405  SignalMappingList* sramB2 = new SignalMappingList;
406  SignalMappingList* sramB3 = new SignalMappingList;
407  sramB0->push_back(new SignalMapping("PIN_AG11","STRATIXII_SRAM_BE_N0"));
408  sramB1->push_back(new SignalMapping("PIN_AK10","STRATIXII_SRAM_BE_N1"));
409  sramB2->push_back(new SignalMapping("PIN_AK11","STRATIXII_SRAM_BE_N2"));
410  sramB3->push_back(new SignalMapping("PIN_AL11","STRATIXII_SRAM_BE_N3"));
411  stratix2Pins_["STRATIXII_SRAM_BE_N0"] = sramB0;
412  stratix2Pins_["STRATIXII_SRAM_BE_N1"] = sramB1;
413  stratix2Pins_["STRATIXII_SRAM_BE_N2"] = sramB2;
414  stratix2Pins_["STRATIXII_SRAM_BE_N3"] = sramB3;
415 }
Netlist.hh
PlatformIntegrator::initPlatformNetlist
virtual void initPlatformNetlist(const ProGe::NetlistBlock *progeBlock)
Definition: PlatformIntegrator.cc:317
Stratix2DSPBoardIntegrator::dmemInstance
virtual MemoryGenerator & dmemInstance(MemInfo dmem, TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
Definition: Stratix2DSPBoardIntegrator.cc:134
FileSystem.hh
ProGe::NetlistBlock
Definition: NetlistBlock.hh:61
machine
TTAMachine::Machine * machine
the architecture definition of the estimated processor
Definition: EstimatorCmdLineUI.cc:59
Exception.hh
SRAM
@ SRAM
Definition: MemoryGenerator.hh:62
MemInfo
Definition: MemoryGenerator.hh:67
Stratix2DSPBoardIntegrator::deviceSpeedClass
virtual TCEString deviceSpeedClass() const
Definition: Stratix2DSPBoardIntegrator.cc:232
Stratix2DSPBoardIntegrator::DEVICE_PACKAGE_
static const TCEString DEVICE_PACKAGE_
Definition: Stratix2DSPBoardIntegrator.hh:118
PlatInt::SignalMappingList
std::vector< SignalMapping * > SignalMappingList
Definition: PlatformIntegratorTypes.hh:44
Stratix2DSPBoardIntegrator::quartusGen_
QuartusProjectGenerator * quartusGen_
Definition: Stratix2DSPBoardIntegrator.hh:108
PlatformIntegrator::writeNewToplevel
virtual void writeNewToplevel()
Definition: PlatformIntegrator.cc:609
PlatformIntegrator::setDeviceName
void setDeviceName(TCEString devName)
Definition: PlatformIntegrator.hh:113
ProjectFileGenerator::writeProjectFiles
virtual void writeProjectFiles()=0
ProGe::Netlist
Definition: Netlist.hh:63
PlatInt::SignalMapping
std::pair< TCEString, TCEString > SignalMapping
Definition: PlatformIntegratorTypes.hh:42
ProGe::NetlistBlock::portCount
virtual size_t portCount() const
Definition: BaseNetlistBlock.cc:248
Stratix2DSPBoardIntegrator::deviceFamily
virtual TCEString deviceFamily() const
Definition: Stratix2DSPBoardIntegrator.cc:207
Stratix2DSPBoardIntegrator::mapToplevelPorts
void mapToplevelPorts()
Definition: Stratix2DSPBoardIntegrator.cc:161
Stratix2DSPBoardIntegrator::PIN_TAG_
static const TCEString PIN_TAG_
Definition: Stratix2DSPBoardIntegrator.hh:122
Stratix2DSPBoardIntegrator.hh
Stratix2DSPBoardIntegrator::devicePackage
virtual TCEString devicePackage() const
Definition: Stratix2DSPBoardIntegrator.cc:225
TTAMachine::FunctionUnit
Definition: FunctionUnit.hh:55
AlteraIntegrator::dmemInstance
virtual MemoryGenerator & dmemInstance(MemInfo dmem, TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
Definition: AlteraIntegrator.cc:134
MemInfo::type
MemType type
Definition: MemoryGenerator.hh:68
InvalidData
Definition: Exception.hh:149
Stratix2SramGenerator
Definition: Stratix2SramGenerator.hh:42
Stratix2DSPBoardIntegrator::DEVICE_FAMILY_
static const TCEString DEVICE_FAMILY_
Definition: Stratix2DSPBoardIntegrator.hh:114
ProjectFileGenerator
Definition: ProjectFileGenerator.hh:41
Stratix2DSPBoardIntegrator::integrateProcessor
virtual void integrateProcessor(const ProGe::NetlistBlock *ttaCore)
Definition: Stratix2DSPBoardIntegrator.cc:111
MemInfo::asName
TCEString asName
Definition: MemoryGenerator.hh:74
NetlistPort.hh
PlatformIntegrator::progeBlock
const ProGe::NetlistBlock & progeBlock() const
Definition: PlatformIntegrator.cc:530
NetlistBlock.hh
Stratix2DSPBoardIntegrator::DEVICE_NAME_
static const TCEString DEVICE_NAME_
Definition: Stratix2DSPBoardIntegrator.hh:116
PlatformIntegrator::targetClockFrequency
virtual int targetClockFrequency() const
Definition: PlatformIntegrator.cc:285
Stratix2DSPBoardIntegrator::addSignalMapping
void addSignalMapping(const TCEString &signal)
Definition: Stratix2DSPBoardIntegrator.cc:169
ProGe::VirtualNetlistBlock
Definition: VirtualNetlistBlock.hh:52
Machine.hh
Stratix2DSPBoardIntegrator::projectFileGenerator
virtual ProjectFileGenerator * projectFileGenerator() const
Definition: Stratix2DSPBoardIntegrator.cc:199
MemoryGenerator::addLsu
void addLsu(TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
Definition: MemoryGenerator.cc:376
MemInfo::widthInMaus
int widthInMaus
Definition: MemoryGenerator.hh:70
Stratix2DSPBoardIntegrator::setDeviceFamily
virtual void setDeviceFamily(TCEString devFamily)
Definition: Stratix2DSPBoardIntegrator.cc:214
ProGe::NetlistPort::name
std::string name() const
Definition: NetlistPort.cc:283
MemInfo::mauWidth
int mauWidth
Definition: MemoryGenerator.hh:69
Stratix2DSPBoardIntegrator::printInfo
virtual void printInfo(std::ostream &stream) const
Definition: Stratix2DSPBoardIntegrator.cc:249
Stratix2DSPBoardIntegrator::~Stratix2DSPBoardIntegrator
virtual ~Stratix2DSPBoardIntegrator()
Definition: Stratix2DSPBoardIntegrator.cc:90
Stratix2DSPBoardIntegrator::dmemGen_
MemoryGenerator * dmemGen_
Definition: Stratix2DSPBoardIntegrator.hh:110
PlatformIntegrator::integratorBlock
ProGe::NetlistBlock * integratorBlock()
Definition: PlatformIntegrator.cc:291
Stratix2DSPBoardIntegrator::Stratix2DSPBoardIntegrator
Stratix2DSPBoardIntegrator()
Definition: Stratix2DSPBoardIntegrator.cc:63
Stratix2SramGenerator.hh
PlatformIntegrator::programName
TCEString programName() const
Definition: PlatformIntegrator.cc:133
Stratix2DSPBoardIntegrator::generatePinMap
void generatePinMap()
Definition: Stratix2DSPBoardIntegrator.cc:268
MemType
MemType
Definition: MemoryGenerator.hh:57
Stratix2DSPBoardIntegrator::stratix2Pins_
PlatInt::PinMap stratix2Pins_
Definition: Stratix2DSPBoardIntegrator.hh:112
QuartusProjectGenerator
Definition: QuartusProjectGenerator.hh:41
ONCHIP
@ ONCHIP
Definition: MemoryGenerator.hh:61
Stratix2DSPBoardIntegrator::DEVICE_SPEED_CLASS_
static const TCEString DEVICE_SPEED_CLASS_
Definition: Stratix2DSPBoardIntegrator.hh:120
TCEString
Definition: TCEString.hh:53
PlatformIntegrator::warningStream
std::ostream & warningStream() const
Definition: PlatformIntegrator.cc:271
PlatformIntegrator::integrateCore
virtual bool integrateCore(const ProGe::NetlistBlock &cores, int coreId)
Definition: PlatformIntegrator.cc:434
Stratix2DSPBoardIntegrator::targetClockFrequency
virtual int targetClockFrequency() const
Definition: Stratix2DSPBoardIntegrator.cc:238
AlteraIntegrator
Definition: AlteraIntegrator.hh:39
VirtualNetlistBlock.hh
Stratix2DSPBoardIntegrator::chopTaggedSignals
virtual bool chopTaggedSignals() const
Definition: Stratix2DSPBoardIntegrator.cc:192
ProGe::HDL
HDL
HDLs supported by ProGe.
Definition: ProGeTypes.hh:40
ProGe::NetlistPort
Definition: NetlistPort.hh:70
MemInfo::portAddrw
int portAddrw
Definition: MemoryGenerator.hh:71
PlatformIntegrator::errorStream
std::ostream & errorStream() const
Definition: PlatformIntegrator.cc:278
PlatformIntegrator::addProGeFiles
void addProGeFiles() const
Definition: PlatformIntegrator.cc:640
Stratix2DSPBoardIntegrator::pinTag
virtual TCEString pinTag() const
Definition: Stratix2DSPBoardIntegrator.cc:185
ProGe::NetlistBlock::port
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
Definition: NetlistBlock.cc:97
IDF::MachineImplementation
Definition: MachineImplementation.hh:54
Stratix2DSPBoardIntegrator::DEFAULT_FREQ_
static const int DEFAULT_FREQ_
Definition: Stratix2DSPBoardIntegrator.hh:124
ProjectFileGenerator::addSignalMapping
void addSignalMapping(const PlatInt::SignalMapping &mapping)
Definition: ProjectFileGenerator.cc:79
TTAMachine::Machine
Definition: Machine.hh:73
MemoryGenerator
Definition: MemoryGenerator.hh:85
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