OpenASIP 2.2
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ProcessorGenerator.hh
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1/*
2 Copyright (c) 2002-2011 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file ProcessorGenerator.hh
26 *
27 * Declaration of ProcessorGenerator class.
28 *
29 * @author Lasse Laasonen 2005 (lasse.laasonen-no.spam-tut.fi)
30 * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
31 * @author Pekka Jääskeläinen 2011
32 * @author Vinogradov Viacheslav(added Verilog generating) 2012
33 * @note rating: red
34 */
35
36#ifndef TTA_PROCESSOR_GENERATOR_HH
37#define TTA_PROCESSOR_GENERATOR_HH
38
39#include "Exception.hh"
40#include "ProGeContext.hh"
41#include "ProGeTypes.hh"
42#include "TCEString.hh"
43#include "ProGeOptions.hh"
44
45
46namespace TTAMachine {
47 class Machine;
48 class FunctionUnit;
49}
50
51namespace IDF {
52 class MachineImplementation;
53}
54
55class BinaryEncoding;
56class FUPortCode;
57
58namespace ProGe {
59
60 class ICDecoderGeneratorPlugin;
61 class Netlist;
62 class NetlistBlock;
63 class NetlistPortGroup;
64 class ProGeContext;
65 class NetlistGenerator;
66
67 /**
68 * Controller class of ProGe.
69 *
70 * Acts as a middle-man between user interface, netlist generator,
71 * IC/decoder
72 * plugin and HDL writers.
73 */
75 public:
77 virtual ~ProcessorGenerator();
78
82 ICDecoderGeneratorPlugin& plugin, int imemWidthInMAUs,
83 std::ostream& errorStream, std::ostream& warningStream,
84 std::ostream& verboseStream);
85
86 static int iMemAddressWidth(const TTAMachine::Machine& mach);
87 static int
88 iMemWidth(const TTAMachine::Machine& mach, int imemWidthInMAUs);
89
90 const NetlistBlock& processorTopLevel() const;
91 const ProGeContext& generatorContext() const;
92
93 TCEString entityName() const;
94
95 static void removeUnconnectedSockets(
96 TTAMachine::Machine& machine, std::ostream& warningStream);
97
98 private:
99 void validateMachine(
100 const TTAMachine::Machine& machine, std::ostream& errorStream,
101 std::ostream& warningStream);
102 void checkIULatencies(
105 const ICDecoderGeneratorPlugin& plugin);
107 HDL language, const TTAMachine::Machine& machine,
108 int imemWidthInMAUs, const std::string& dstDirectory,
110 void generateGCUOpcodesPackage(HDL language,
112 const std::string& dstDirectory);
113 static std::string coreIdString(int i);
114 static const NetlistPortGroup* instructionBus(NetlistBlock& block);
115
119
121 };
122}
123
124#endif
IDF::MachineImplementation * implementation
the implementation definition of the estimated processor
TTAMachine::Machine * machine
the architecture definition of the estimated processor
static MachInfoCmdLineOptions options
Definition MachInfo.cc:46
const ProGeContext & generatorContext() const
static int iMemWidth(const TTAMachine::Machine &mach, int imemWidthInMAUs)
void generateGCUOpcodesPackage(HDL language, const TTAMachine::Machine &machine, const std::string &dstDirectory)
void generateGlobalsPackage(HDL language, const TTAMachine::Machine &machine, int imemWidthInMAUs, const std::string &dstDirectory, ICDecoderGeneratorPlugin &plugin)
void validateMachine(const TTAMachine::Machine &machine, std::ostream &errorStream, std::ostream &warningStream)
static std::string coreIdString(int i)
void checkIULatencies(const TTAMachine::Machine &machine, const IDF::MachineImplementation &implementation, const ICDecoderGeneratorPlugin &plugin)
static void removeUnconnectedSockets(TTAMachine::Machine &machine, std::ostream &warningStream)
const NetlistBlock & processorTopLevel() const
static int iMemAddressWidth(const TTAMachine::Machine &mach)
void generateProcessor(const ProGeOptions &options, const TTAMachine::Machine &machine, const IDF::MachineImplementation &implementation, ICDecoderGeneratorPlugin &plugin, int imemWidthInMAUs, std::ostream &errorStream, std::ostream &warningStream, std::ostream &verboseStream)
static const NetlistPortGroup * instructionBus(NetlistBlock &block)
static const TCEString DEFAULT_ENTITY_STR
Definition FUGen.hh:54
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40