ProGe::ProcessorGenerator Class Reference

#include <ProcessorGenerator.hh>

Collaboration diagram for ProGe::ProcessorGenerator:

Public Member Functions
	ProcessorGenerator ()
virtual	~ProcessorGenerator ()
void	generateProcessor (const ProGeOptions &options, const TTAMachine::Machine &machine, const IDF::MachineImplementation &implementation, ICDecoderGeneratorPlugin &plugin, int imemWidthInMAUs, std::ostream &errorStream, std::ostream &warningStream, std::ostream &verboseStream)
const NetlistBlock &	processorTopLevel () const
const ProGeContext &	generatorContext () const
TCEString	entityName () const

Static Public Member Functions
static int	iMemAddressWidth (const TTAMachine::Machine &mach)
static int	iMemWidth (const TTAMachine::Machine &mach, int imemWidthInMAUs)
static void	removeUnconnectedSockets (TTAMachine::Machine &machine, std::ostream &warningStream)

Private Member Functions
void	validateMachine (const TTAMachine::Machine &machine, std::ostream &errorStream, std::ostream &warningStream)
void	checkIULatencies (const TTAMachine::Machine &machine, const IDF::MachineImplementation &implementation, const ICDecoderGeneratorPlugin &plugin)
void	generateGlobalsPackage (HDL language, const TTAMachine::Machine &machine, int imemWidthInMAUs, const std::string &dstDirectory, ICDecoderGeneratorPlugin &plugin)
void	generateGCUOpcodesPackage (HDL language, const TTAMachine::Machine &machine, const std::string &dstDirectory)

Static Private Member Functions
static std::string	coreIdString (int i)
static const NetlistPortGroup *	instructionBus (NetlistBlock &block)

Private Attributes
NetlistBlock *	coreTopBlock_
TCEString	entityStr_
ProGeContext *	generatorContext_

Static Private Attributes
static const TCEString	DEFAULT_ENTITY_STR = "tta0"

Detailed Description

Controller class of ProGe.

Acts as a middle-man between user interface, netlist generator, IC/decoder plugin and HDL writers.

Definition at line 74 of file ProcessorGenerator.hh.

Constructor & Destructor Documentation

ProcessorGenerator()

ProGe::ProcessorGenerator::ProcessorGenerator

(

)

The constructor.

Definition at line 114 of file ProcessorGenerator.cc.

: coreTopBlock_(NULL) {}

~ProcessorGenerator()

ProGe::ProcessorGenerator::~ProcessorGenerator ( )

virtual

The destructor.

Definition at line 119 of file ProcessorGenerator.cc.

                                        {
    delete coreTopBlock_;
    coreTopBlock_ = NULL;
}

References coreTopBlock_.

Member Function Documentation

checkIULatencies()

void ProGe::ProcessorGenerator::checkIULatencies ( const TTAMachine::Machine &  machine, const IDF::MachineImplementation &  implementation, const ICDecoderGeneratorPlugin &  plugin  )

private

Checks that the latencies of the HW implementations of the immediate units are compatible with the given IC/GCU generator plugin.

Parameters

machine	The machine.
implementation	The machine implementation.
plugin	The plugin.

Exceptions

InvalidData

If the latencies are incompatible.

Definition at line 390 of file ProcessorGenerator.cc.

                                            {
    Machine::ImmediateUnitNavigator iuNav = machine.immediateUnitNavigator();
    for (int i = 0; i < iuNav.count(); i++) {
        ImmediateUnit* iu = iuNav.item(i);
        RFImplementationLocation& impl =
            implementation.iuImplementation(iu->name());
 
        RFEntry* entry = NULL;
        try {
            HDBManager& manager = HDBRegistry::instance().hdb(impl.hdbFile());
            entry = manager.rfByEntryID(impl.id());
        } catch (const KeyNotFound& e) {
            throw InvalidData(__FILE__, __LINE__, __func__, e.errorMessage());
        }
 
        if (!entry->hasArchitecture()) {
            delete entry;
            format text(
                "RF entry %1% does not have architecture defined in HDB "
                "%2%.");
            text % impl.id() % impl.hdbFile();
            throw InvalidData(__FILE__, __LINE__, __func__, text.str());
        }
 
        RFArchitecture& architecture = entry->architecture();
        int implLatency = architecture.latency();
        std::set<int> requiredLatencies = plugin.requiredRFLatencies(*iu);
        delete entry;
 
        if (requiredLatencies.count(implLatency) == 0) {
            format errorMsg(
                "Latency of the implementation of immediate "
                "unit %1% is %2%,"
                " acceptable latencies are %3%.");
            errorMsg % iu->name() % implLatency %
                TCEString::makeString(requiredLatencies);
            throw InvalidData(__FILE__, __LINE__, __func__, errorMsg.str());
        }
    }
}

References __func__, HDB::RFEntry::architecture(), TTAMachine::Machine::Navigator< ComponentType >::count(), Exception::errorMessage(), HDB::RFEntry::hasArchitecture(), HDB::HDBRegistry::hdb(), IDF::UnitImplementationLocation::hdbFile(), IDF::UnitImplementationLocation::id(), TTAMachine::Machine::immediateUnitNavigator(), implementation, HDB::HDBRegistry::instance(), TTAMachine::Machine::Navigator< ComponentType >::item(), IDF::MachineImplementation::iuImplementation(), HDB::RFArchitecture::latency(), machine, TCEString::makeString(), TTAMachine::Component::name(), ProGe::ICDecoderGeneratorPlugin::requiredRFLatencies(), and HDB::HDBManager::rfByEntryID().

Referenced by generateProcessor().

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coreIdString()

static std::string ProGe::ProcessorGenerator::coreIdString ( int  i )

staticprivate

entityName()

TCEString ProGe::ProcessorGenerator::entityName

(

)

const

Definition at line 524 of file ProcessorGenerator.cc.

                                     {
    return entityStr_;
}

References entityStr_.

Referenced by generateGlobalsPackage().

generateGCUOpcodesPackage()

void ProGe::ProcessorGenerator::generateGCUOpcodesPackage ( HDL  language, const TTAMachine::Machine &  machine, const std::string &  dstDirectory  )

private

Generates the package that defines opcodes of Global Control Unit.

Parameters

language	The language of the hardware code, VHDL/Verilog
machine	The machine.
dstDirectory	The destination directory.

Definition at line 306 of file ProcessorGenerator.cc.

                                   {
    string dstFile = dstDirectory + FileSystem::DIRECTORY_SEPARATOR +
                     "gcu_opcodes_pkg." +
                     ((language == ProGe::VHDL) ? "vhdl" : "vh");
    std::ofstream stream(dstFile.c_str(), std::ofstream::out);
    CUOpcodeGenerator gcuOpcodeGen(machine, entityStr_);
    gcuOpcodeGen.generateOpcodePackage(language, stream);
    stream.close();
}

References FileSystem::DIRECTORY_SEPARATOR, entityStr_, ProGe::CUOpcodeGenerator::generateOpcodePackage(), machine, and ProGe::VHDL.

Referenced by generateProcessor().

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generateGlobalsPackage()

void ProGe::ProcessorGenerator::generateGlobalsPackage ( HDL  language, const TTAMachine::Machine &  machine, int  imemWidthInMAUs, const std::string &  dstDirectory, ICDecoderGeneratorPlugin &  plugin  )

private

Generates the package that defines global constants used in processor definition files.

Parameters

language	The language of the hardware code, VHDL/Verilog
machine	The machine.
imemWidthInMAUs	Width of the instruction memory in MAUs.
dstDirectory	The destination directory.
plugin	The ICDecoderGeneratorPlugin, which gives us bem and bit info

Exceptions

IOException

If an IO error occurs.

Definition at line 230 of file ProcessorGenerator.cc.

                                                                     {
    string dstFile = dstDirectory + FileSystem::DIRECTORY_SEPARATOR +
                     entityName() + "_globals_pkg." +
                     ((language == ProGe::VHDL) ? "vhdl" : "vh");
 
    bool created = FileSystem::createFile(dstFile);
    if (!created) {
        string errorMsg = "Unable to create file " + dstFile;
        throw IOException(__FILE__, __LINE__, __func__, errorMsg);
    }
    std::ofstream stream(dstFile.c_str(), std::ofstream::out);
 
    if (language == ProGe::VHDL) {
        int bustrace_width = 0;
        for (int i = 0; i < machine.busNavigator().count(); ++i) {
            int bus_width = machine.busNavigator().item(i)->width();
            // Busess are padded to a multiple of 32 bits
            bus_width = (bus_width + 31) / 32 * 32;
            bustrace_width += bus_width;
        }
 
        stream << "library work;" << endl
               << "use work." << entityStr_ << "_imem_mau.all;" << endl
               << endl;
 
        stream << "package " << entityStr_ << "_globals is" << endl
               << "  -- address width of the instruction memory" << endl
               << "  constant IMEMADDRWIDTH : positive := "
               << iMemAddressWidth(machine) << ";" << endl
               << "  -- width of the instruction memory in MAUs" << endl
               << "  constant IMEMWIDTHINMAUS : positive := "
               << imemWidthInMAUs << ";" << endl
               << "  -- width of instruction fetch block." << endl
               << "  constant IMEMDATAWIDTH : positive := "
               << "IMEMWIDTHINMAUS*IMEMMAUWIDTH;" << endl
               << "  -- clock period" << endl
               << "  constant PERIOD : time := 10 ns;" << endl
               << "  -- number of busses." << endl
               << "  constant BUSTRACE_WIDTH : positive := " << bustrace_width
               << ";" << endl;
 
        // Insert plugin specific global package constants
        plugin.writeGlobalDefinitions(ProGe::VHDL, stream);
 
        stream << "end " << entityStr_ << "_globals;" << endl;
 
    } else if (language == ProGe::Verilog) {
        // todo add IMEMDATAWIDTH constant here too.
 
        stream << "// address width of the instruction memory" << endl
               << "parameter IMEMADDRWIDTH = " << iMemAddressWidth(machine)
               << "," << endl
               << "// width of the instruction memory in MAUs" << endl
               << "parameter IMEMWIDTHINMAUS = " << imemWidthInMAUs << ","
               << endl
               << "// clock period" << endl
               << "parameter PERIOD = 10," << endl;  // 10 will equal 10ns
 
        plugin.writeGlobalDefinitions(ProGe::Verilog, stream);
 
    } else {
        abortWithError("Unsupported HDL.");
    }
    stream.close();
}

References __func__, abortWithError, TTAMachine::Machine::busNavigator(), FileSystem::createFile(), FileSystem::DIRECTORY_SEPARATOR, entityName(), entityStr_, iMemAddressWidth(), TTAMachine::Machine::Navigator< ComponentType >::item(), machine, ProGe::Verilog, ProGe::VHDL, and ProGe::ICDecoderGeneratorPlugin::writeGlobalDefinitions().

Referenced by generateProcessor().

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generateProcessor()

void ProGe::ProcessorGenerator::generateProcessor	(	const ProGeOptions &	options,
		const TTAMachine::Machine &	machine,
		const IDF::MachineImplementation &	implementation,
		ICDecoderGeneratorPlugin &	plugin,
		int	imemWidthInMAUs,
		std::ostream &	errorStream,
		std::ostream &	warningStream,
		std::ostream &	verboseStream
	)

Generates the processor.

See also

ProGeUI::generateProcessor()

Definition at line 130 of file ProcessorGenerator.cc.

                               {
    entityStr_ = options.entityName;
    generatorContext_ = new ProGeContext(
        machine, implementation, options.outputDirectory,
        options.sharedOutputDirectory, options.entityName, options.language,
        imemWidthInMAUs);
 
    // validate the machine
    validateMachine(machine, errorStream, warningStream);
    // check the compatibility of the plugin
    plugin.verifyCompatibility();
    // check that IU implementation latencies are compatible with the
    // IC/GCU plugin
    checkIULatencies(machine, implementation, plugin);
 
    NetlistGenerator netlistGenerator(*generatorContext_, plugin);
    coreTopBlock_ = netlistGenerator.generate(
        options, imemWidthInMAUs, options.entityName, warningStream);
 
    bool created = FileSystem::createDirectory(options.outputDirectory);
    if (!created) {
        string errorMsg =
            "Unable to create directory " + options.outputDirectory;
        throw IOException(__FILE__, __LINE__, __func__, errorMsg);
    }
 
    string pluginDstDir =
        options.outputDirectory + FileSystem::DIRECTORY_SEPARATOR + "gcu_ic";
    created = FileSystem::createDirectory(pluginDstDir);
    if (!created) {
        string errorMsg = "Unable to create directory " + pluginDstDir;
        throw IOException(__FILE__, __LINE__, __func__, errorMsg);
    }
 
    plugin.generate(
        options.language, pluginDstDir, netlistGenerator, implementation,
        options.entityName);
 
    // Generate generatable FU implementations.
    std::vector<std::string> globalOptions;
    globalOptions.emplace_back("active low reset");
    globalOptions.emplace_back("asynchronous reset");
    globalOptions.emplace_back("reset everything");
    FUGen::implement(
        options, globalOptions, generatorContext_->idf().FUGenerations(),
        generatorContext_->adf(), coreTopBlock_);
 
    coreTopBlock_->write(Path(options.outputDirectory), options.language);
 
    string topLevelDir = options.outputDirectory +
                         FileSystem::DIRECTORY_SEPARATOR +
                         (options.language == VHDL ? "vhdl" : "verilog");
 
    if (Application::spamVerbose())
        NetlistVisualization::visualizeBlockTree(
            *coreTopBlock_, verboseStream);
 
    if (!FileSystem::fileExists(options.sharedOutputDirectory)) {
        if (!FileSystem::createDirectory(options.sharedOutputDirectory)) {
            string errorMsg = "Unable to create directory " +
                              options.sharedOutputDirectory + ".";
            throw IOException(__FILE__, __LINE__, __func__, errorMsg);
        }
    }
    BlockSourceCopier copier(
        implementation, options.entityName, options.language);
 
    if (machine.isRISCVMachine()) {
        copier.getTemplateInstatiator().replacePlaceholder(
            "decomp-fetchblock-width", "INSTRUCTIONWIDTH");
    }
 
    copier.copyShared(options.sharedOutputDirectory);
    copier.copyProcessorSpecific(options.outputDirectory);
    generateGCUOpcodesPackage(
        options.language, machine,
        options.outputDirectory + FileSystem::DIRECTORY_SEPARATOR + "gcu_ic");
 
    generateGlobalsPackage(
        options.language, machine, imemWidthInMAUs, topLevelDir, plugin);
}

References __func__, ProGe::ProGeContext::adf(), checkIULatencies(), ProGe::BlockSourceCopier::copyProcessorSpecific(), ProGe::BlockSourceCopier::copyShared(), coreTopBlock_, FileSystem::createDirectory(), FileSystem::DIRECTORY_SEPARATOR, entityStr_, FileSystem::fileExists(), IDF::MachineImplementation::FUGenerations(), ProGe::NetlistGenerator::generate(), ProGe::ICDecoderGeneratorPlugin::generate(), generateGCUOpcodesPackage(), generateGlobalsPackage(), generatorContext_, ProGe::BlockSourceCopier::getTemplateInstatiator(), ProGe::ProGeContext::idf(), FUGen::implement(), implementation, TTAMachine::Machine::isRISCVMachine(), machine, options, HDLTemplateInstantiator::replacePlaceholder(), Application::spamVerbose(), validateMachine(), ProGe::ICDecoderGeneratorPlugin::verifyCompatibility(), ProGe::VHDL, ProGe::NetlistVisualization::visualizeBlockTree(), and ProGe::NetlistBlock::write().

Referenced by ProGe::ProGeUI::generateProcessor().

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generatorContext()

const ProGeContext & ProGe::ProcessorGenerator::generatorContext

(

)

const

Returns the context (adf, idf, entity name, etc.) that is used in the processor generation.

Definition at line 519 of file ProcessorGenerator.cc.

                                           {
    return *generatorContext_;
}

References generatorContext_.

Referenced by ProGe::ProGeUI::generateTestBench().

iMemAddressWidth()

int ProGe::ProcessorGenerator::iMemAddressWidth ( const TTAMachine::Machine &  mach )

static

Returns the width of the memory address of instruction memory of the given machine.

If the memory address width set in machine instruction memory address space differ from gcu port widths, the value set in the address space is used. In this case, GCU port widths are changed accordingly.

Parameters

mach	The machine.

Returns

The bit width.

Exceptions

InvalidData

If the GCU of the machine does not have an address space.

Definition at line 449 of file ProcessorGenerator.cc.

                                                                  {
    ControlUnit* gcu = mach.controlUnit();
    // must have been already caught in main method: generateProcessor
    assert(gcu != NULL);
 
    AddressSpace* iMem = gcu->addressSpace();
    // must have been already caught in main method: generateProcessor
    assert(iMem != NULL);
 
    int imemASWidth = MathTools::requiredBits(iMem->end());
    // if gcu port have different width than imemASWidth, change port
    // widths
    if (gcu->hasReturnAddressPort()) {
        int gcuRAPortWidth = gcu->returnAddressPort()->width();
        if (gcuRAPortWidth != imemASWidth) {
            gcu->returnAddressPort()->setWidth(imemASWidth);
        }
    }
    if (gcu->hasOperation(CALL)) {
        FUPort* pcPort = gcu->operation(CALL)->port(1);
        if (pcPort != NULL) {
            if (pcPort->width() != imemASWidth) {
                pcPort->setWidth(imemASWidth);
            }
        }
    } else if (gcu->hasOperation(JUMP)) {
        FUPort* pcPort = gcu->operation(JUMP)->port(1);
        if (pcPort != NULL) {
            if (pcPort->width() != imemASWidth) {
                pcPort->setWidth(imemASWidth);
            }
        }
    }
 
    return imemASWidth;
}

References TTAMachine::FunctionUnit::addressSpace(), assert, CALL, TTAMachine::Machine::controlUnit(), TTAMachine::AddressSpace::end(), TTAMachine::FunctionUnit::hasOperation(), TTAMachine::ControlUnit::hasReturnAddressPort(), JUMP, TTAMachine::FunctionUnit::operation(), TTAMachine::HWOperation::port(), MathTools::requiredBits(), TTAMachine::ControlUnit::returnAddressPort(), TTAMachine::BaseFUPort::setWidth(), and TTAMachine::BaseFUPort::width().

Referenced by generateGlobalsPackage().

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iMemWidth()

int ProGe::ProcessorGenerator::iMemWidth ( const TTAMachine::Machine &  mach, int  imemWidthInMAUs  )

static

Returns the width of the instruction memory of the given machine.

Parameters

mach	The machine.

Returns

The bit width.

Definition at line 493 of file ProcessorGenerator.cc.

                                                        {
    ControlUnit* gcu = mach.controlUnit();
    // must have been already caught in main method: generateProcessor
    assert(gcu != NULL);
 
    AddressSpace* iMem = gcu->addressSpace();
    // must have been already caught in main method: generateProcessor
    assert(iMem != NULL);
 
    return iMem->width() * imemWidthInMAUs;
}

References TTAMachine::FunctionUnit::addressSpace(), assert, TTAMachine::Machine::controlUnit(), and TTAMachine::AddressSpace::width().

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instructionBus()

const NetlistPortGroup * ProGe::ProcessorGenerator::instructionBus ( NetlistBlock &  block )

staticprivate

Definition at line 319 of file ProcessorGenerator.cc.

                                                      {
    assert(!block.portGroupsBy(SignalGroupType::INSTRUCTION_LINE).empty());
    return block.portGroupsBy(SignalGroupType::INSTRUCTION_LINE).at(0);
}

References assert, ProGe::INSTRUCTION_LINE, and ProGe::BaseNetlistBlock::portGroupsBy().

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processorTopLevel()

const NetlistBlock & ProGe::ProcessorGenerator::processorTopLevel

(

)

const

Returns Toplevel block of the core.

Definition at line 510 of file ProcessorGenerator.cc.

                                            {
    return *coreTopBlock_;
}

References coreTopBlock_.

Referenced by ProGe::ProGeUI::generateTestBench(), and ProGe::ProGeUI::integrateProcessor().

removeUnconnectedSockets()

void ProGe::ProcessorGenerator::removeUnconnectedSockets ( TTAMachine::Machine &  machine, std::ostream &  warningStream  )

static

Definition at line 529 of file ProcessorGenerator.cc.

                                                           {
    MachineResourceModifier modifier;
    std::list<string> removedSockets;
    modifier.removeNotConnectedSockets(machine, removedSockets);
 
    for (std::list<string>::iterator i = removedSockets.begin();
         i != removedSockets.end(); i++) {
        warningStream << "Warning: Removed unconnected socket " << *i
                      << std::endl;
    }
}

References machine, and MachineResourceModifier::removeNotConnectedSockets().

Referenced by ProGe::ProGeUI::generateProcessor().

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validateMachine()

void ProGe::ProcessorGenerator::validateMachine ( const TTAMachine::Machine &  machine, std::ostream &  errorStream, std::ostream &  warningStream  )

private

Validates the machine for compatibility with the given block implementations.

If the target architecture contains errors (incomplete definition) or if its structure is not compatible with this HDL generator, this method throws IllegalMachine exception. For less serious errors (such as non-critical bit width discrepancies), warning messages are written to the given stream.

Parameters

machine	The machine to validate.
errorStream	Output stream where errors are printed
warningStream	Output stream where warnings are printed

Exceptions

IllegalMachine

If there is a fundamental error in the machine.

Definition at line 341 of file ProcessorGenerator.cc.

                               {
    MachineValidator validator(machine);
    set<MachineValidator::ErrorCode> errorsToCheck;
    errorsToCheck.insert(MachineValidator::GCU_MISSING);
    errorsToCheck.insert(MachineValidator::GCU_AS_MISSING);
    errorsToCheck.insert(MachineValidator::USED_IO_NOT_BOUND);
    errorsToCheck.insert(MachineValidator::DIFFERENT_PORT_FOR_JUMP_AND_CALL);
    errorsToCheck.insert(MachineValidator::PC_PORT_MISSING);
    errorsToCheck.insert(MachineValidator::RA_PORT_MISSING);
    errorsToCheck.insert(
        MachineValidator::PC_AND_RA_PORTS_HAVE_UNEQUAL_WIDTH);
    // we should not check for this as the designer is not supposed to
    // know the width of these ports before the design has been finalized,
    // thus we generate them automatically in ProGe
    // errorsToCheck.insert(
    //    MachineValidator::IMEM_ADDR_WIDTH_DIFFERS_FROM_RA_AND_PC);
 
    MachineValidatorResults* results = validator.validate(errorsToCheck);
 
    for (int i = 0; i < results->errorCount(); i++) {
        MachineValidator::ErrorCode code = results->error(i).first;
        string errorMsg = results->error(i).second;
        if (code ==
            MachineValidator::IMEM_ADDR_WIDTH_DIFFERS_FROM_RA_AND_PC) {
            warningStream << "Warning: " << errorMsg
                          << " ProGe uses the value set in the address space."
                          << endl;
        } else {
            string msg = "Error: " + errorMsg;
            errorStream << msg << std::endl;
            delete results;
            throw IllegalMachine(__FILE__, __LINE__, __func__, msg);
        }
    }
    delete results;
}

References __func__, MachineValidator::DIFFERENT_PORT_FOR_JUMP_AND_CALL, MachineValidatorResults::error(), MachineValidatorResults::errorCount(), MachineValidator::GCU_AS_MISSING, MachineValidator::GCU_MISSING, MachineValidator::IMEM_ADDR_WIDTH_DIFFERS_FROM_RA_AND_PC, machine, MachineValidator::PC_AND_RA_PORTS_HAVE_UNEQUAL_WIDTH, MachineValidator::PC_PORT_MISSING, MachineValidator::RA_PORT_MISSING, MachineValidator::USED_IO_NOT_BOUND, and MachineValidator::validate().

Referenced by generateProcessor().

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Member Data Documentation

coreTopBlock_

NetlistBlock* ProGe::ProcessorGenerator::coreTopBlock_

private

Definition at line 116 of file ProcessorGenerator.hh.

Referenced by generateProcessor(), processorTopLevel(), and ~ProcessorGenerator().

DEFAULT_ENTITY_STR

const TCEString ProGe::ProcessorGenerator::DEFAULT_ENTITY_STR = "tta0"

staticprivate

Definition at line 120 of file ProcessorGenerator.hh.

entityStr_

TCEString ProGe::ProcessorGenerator::entityStr_

private

Definition at line 117 of file ProcessorGenerator.hh.

Referenced by entityName(), generateGCUOpcodesPackage(), generateGlobalsPackage(), and generateProcessor().

generatorContext_

ProGeContext* ProGe::ProcessorGenerator::generatorContext_

private

Definition at line 118 of file ProcessorGenerator.hh.

Referenced by generateProcessor(), and generatorContext().

---

The documentation for this class was generated from the following files:

• ProcessorGenerator.hh
• ProcessorGenerator.cc