OpenASIP 2.2
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Stratix3DevKitIntegrator.cc
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1/*
2 Copyright (c) 2002-2011 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file Stratix3DevKitIntegrator.hh
26 *
27 * Implementation of Stratix3DevKitIntegrator class.
28 *
29 * @author Otto Esko 2011 (otto.esko-no.spam-tut.fi)
30 * @note rating: red
31 */
32
33#include "Exception.hh"
35#include "Netlist.hh"
36#include "NetlistPort.hh"
37#include "NetlistBlock.hh"
38using ProGe::Netlist;
43using std::vector;
44using std::endl;
45
47
49
51
53
55
57
58
62
63
67 ProGe::HDL hdl,
68 TCEString progeOutputDir,
69 TCEString coreEntityName,
70 TCEString outputDir,
71 TCEString programName,
72 int targetClockFreq,
73 std::ostream& warningStream,
74 std::ostream& errorStream,
75 const MemInfo& imem,
76 MemType dmemType):
77 AlteraIntegrator(machine, idf, hdl, progeOutputDir, coreEntityName,
78 outputDir, programName, targetClockFreq, warningStream,
79 errorStream, imem, dmemType),
80 quartusGen_(new QuartusProjectGenerator(coreEntityName, this)) {
82}
83
84
86
87 for (PlatInt::PinMap::iterator iter = stratix3Pins_.begin();
88 iter != stratix3Pins_.end(); iter++) {
89 if (iter->second != NULL) {
90 for (unsigned int i = 0; i < iter->second->size(); i++) {
91 delete iter->second->at(i);
92 }
93 delete iter->second;
94 }
95 }
96 if (quartusGen_ != NULL) {
97 delete quartusGen_;
98 }
99}
100
101
102void
104 const ProGe::NetlistBlock* ttaCore) {
105
107
108 initPlatformNetlist(ttaCore);
109
110 const NetlistBlock& core = progeBlock();
111 int coreId = -1;
112 if (!integrateCore(core, coreId)) {
113 return;
114 }
115
117
119
121
123}
124
125
131
132
133void
135
136 if (devFamily != DEVICE_FAMILY_) {
138 << "Warning: Refusing to change device family!" << endl
139 << "- Original device family: " << DEVICE_FAMILY_ << endl
140 << "- New device family: " << devFamily << endl;
141 }
142}
143
144
150
151
157
158
159int
161
162 int freq = DEFAULT_FREQ_;
163
166 }
167 return freq;
168}
169
170
171void
172Stratix3DevKitIntegrator::printInfo(std::ostream& stream) const {
173
174 stream
175 << "Integrator name: Stratix3DevKit" << std::endl
176 << "---------------------------------" << std::endl
177 << "Integrates TTA core to Altera Stratix III Development Kit"
178 << std::endl << "with" << DEVICE_NAME_ << " device." << std::endl
179 << "Creates project files for QuartusII v8.0 program." << std::endl
180 << "Supported instruction memory types are 'onchip' and 'vhdl_array."
181 << std::endl
182 << "Supported data memory type is 'onchip'."
183 << std::endl
184 << "Default clock frequency is 125 MHz." << std::endl
185 << "Active low reset is connected to CPU RESET button."
186 << std::endl << std::endl;
187}
188
189
192
193 return PIN_TAG_;
194}
195
196
197bool
199
200 return true;
201}
202
203
209
210
211void
214 for (size_t i = 0; i < tl.portCount(); i++) {
215 addSignalMapping(tl.port(i).name());
216 }
217}
218
219
220void
222
223 if (stratix3Pins_.find(signal) == stratix3Pins_.end()) {
224 warningStream() << "Warning: didn't find mapping for signal name "
225 << signal << endl;
226 return;
227 }
228
229 SignalMappingList* mappings = stratix3Pins_.find(signal)->second;
230 for (unsigned int i = 0; i < mappings->size(); i++) {
231 quartusGen_->addSignalMapping(*mappings->at(i));
232 }
233}
234
235
236void
238
239 // clk
240 SignalMappingList* clk = new SignalMappingList;
241 clk->push_back(new SignalMapping("PIN_B16","clk"));
242 stratix3Pins_["clk"] = clk;
243
244 // reset to push button CPU_RESET
245 SignalMappingList* rstx = new SignalMappingList;
246 rstx->push_back(new SignalMapping("PIN_AP5","rstx"));
247 stratix3Pins_["rstx"] = rstx;
248
249 // leds
250 const TCEString led = PIN_TAG_+"_LED";
251 SignalMappingList* ledMapping = new SignalMappingList;
252 ledMapping->push_back(new SignalMapping("PIN_F21", led+"[0]"));
253 ledMapping->push_back(new SignalMapping("PIN_C23", led+"[1]"));
254 ledMapping->push_back(new SignalMapping("PIN_B23", led+"[2]"));
255 ledMapping->push_back(new SignalMapping("PIN_A23", led+"[3]"));
256 ledMapping->push_back(new SignalMapping("PIN_D19", led+"[4]"));
257 ledMapping->push_back(new SignalMapping("PIN_C19", led+"[5]"));
258 ledMapping->push_back(new SignalMapping("PIN_F19", led+"[6]"));
259 ledMapping->push_back(new SignalMapping("PIN_E19", led+"[7]"));
260 stratix3Pins_[led] = ledMapping;
261
262 // dip switches
263 const TCEString sw = PIN_TAG_+"_USER_DIPSW";
264 SignalMappingList* switchMapping = new SignalMappingList;
265 switchMapping->push_back(new SignalMapping("PIN_B19", sw+"[0]"));
266 switchMapping->push_back(new SignalMapping("PIN_A19", sw+"[1]"));
267 switchMapping->push_back(new SignalMapping("PIN_C18", sw+"[2]"));
268 switchMapping->push_back(new SignalMapping("PIN_A20", sw+"[3]"));
269 switchMapping->push_back(new SignalMapping("PIN_K19", sw+"[4]"));
270 switchMapping->push_back(new SignalMapping("PIN_J19", sw+"[5]"));
271 switchMapping->push_back(new SignalMapping("PIN_L19", sw+"[6]"));
272 switchMapping->push_back(new SignalMapping("PIN_L20", sw+"[7]"));
273 stratix3Pins_[sw] = switchMapping;
274
275 // push buttons
276 const TCEString pb = PIN_TAG_+"_USER_PB";
277 SignalMappingList* pbMapping = new SignalMappingList;
278 pbMapping->push_back(new SignalMapping("PIN_B17", pb+"[0]"));
279 pbMapping->push_back(new SignalMapping("PIN_A17", pb+"[1]"));
280 pbMapping->push_back(new SignalMapping("PIN_A16", pb+"[2]"));
281 pbMapping->push_back(new SignalMapping("PIN_K17", pb+"[3]"));
282 stratix3Pins_[pb] = pbMapping;
283
284}
TTAMachine::Machine * machine
the architecture definition of the estimated processor
virtual void initPlatformNetlist(const ProGe::NetlistBlock *progeBlock)
std::ostream & warningStream() const
virtual int targetClockFrequency() const
ProGe::NetlistBlock * integratorBlock()
virtual bool integrateCore(const ProGe::NetlistBlock &cores, int coreId)
const ProGe::NetlistBlock & progeBlock() const
void setDeviceName(TCEString devName)
virtual void writeNewToplevel()
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
virtual size_t portCount() const
std::string name() const
void addSignalMapping(const PlatInt::SignalMapping &mapping)
virtual void writeProjectFiles()=0
virtual ProjectFileGenerator * projectFileGenerator() const
virtual void integrateProcessor(const ProGe::NetlistBlock *ttaCore)
virtual void setDeviceFamily(TCEString devFamily)
static const TCEString DEVICE_FAMILY_
static const TCEString DEVICE_SPEED_CLASS_
static const TCEString DEVICE_PACKAGE_
virtual void printInfo(std::ostream &stream) const
virtual TCEString deviceSpeedClass() const
virtual TCEString devicePackage() const
QuartusProjectGenerator * quartusGen_
static const TCEString DEVICE_NAME_
virtual TCEString deviceFamily() const
void addSignalMapping(const TCEString &signal)
virtual TCEString pinTag() const
std::vector< SignalMapping * > SignalMappingList
std::pair< TCEString, TCEString > SignalMapping
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40