73 std::ostream& warningStream,
74 std::ostream& errorStream,
78 outputDir, programName, targetClockFreq, warningStream,
79 errorStream, imem, dmemType),
89 if (iter->second != NULL) {
90 for (
unsigned int i = 0; i < iter->second->size(); i++) {
91 delete iter->second->at(i);
138 <<
"Warning: Refusing to change device family!" << endl
140 <<
"- New device family: " << devFamily << endl;
175 <<
"Integrator name: Stratix3DevKit" << std::endl
176 <<
"---------------------------------" << std::endl
177 <<
"Integrates TTA core to Altera Stratix III Development Kit"
178 << std::endl <<
"with" <<
DEVICE_NAME_ <<
" device." << std::endl
179 <<
"Creates project files for QuartusII v8.0 program." << std::endl
180 <<
"Supported instruction memory types are 'onchip' and 'vhdl_array."
182 <<
"Supported data memory type is 'onchip'."
184 <<
"Default clock frequency is 125 MHz." << std::endl
185 <<
"Active low reset is connected to CPU RESET button."
186 << std::endl << std::endl;
214 for (
size_t i = 0; i < tl.
portCount(); i++) {
224 warningStream() <<
"Warning: didn't find mapping for signal name "
229 SignalMappingList* mappings =
stratix3Pins_.find(signal)->second;
230 for (
unsigned int i = 0; i < mappings->size(); i++) {
240 SignalMappingList* clk =
new SignalMappingList;
241 clk->push_back(
new SignalMapping(
"PIN_B16",
"clk"));
245 SignalMappingList* rstx =
new SignalMappingList;
246 rstx->push_back(
new SignalMapping(
"PIN_AP5",
"rstx"));
251 SignalMappingList* ledMapping =
new SignalMappingList;
252 ledMapping->push_back(
new SignalMapping(
"PIN_F21", led+
"[0]"));
253 ledMapping->push_back(
new SignalMapping(
"PIN_C23", led+
"[1]"));
254 ledMapping->push_back(
new SignalMapping(
"PIN_B23", led+
"[2]"));
255 ledMapping->push_back(
new SignalMapping(
"PIN_A23", led+
"[3]"));
256 ledMapping->push_back(
new SignalMapping(
"PIN_D19", led+
"[4]"));
257 ledMapping->push_back(
new SignalMapping(
"PIN_C19", led+
"[5]"));
258 ledMapping->push_back(
new SignalMapping(
"PIN_F19", led+
"[6]"));
259 ledMapping->push_back(
new SignalMapping(
"PIN_E19", led+
"[7]"));
264 SignalMappingList* switchMapping =
new SignalMappingList;
265 switchMapping->push_back(
new SignalMapping(
"PIN_B19", sw+
"[0]"));
266 switchMapping->push_back(
new SignalMapping(
"PIN_A19", sw+
"[1]"));
267 switchMapping->push_back(
new SignalMapping(
"PIN_C18", sw+
"[2]"));
268 switchMapping->push_back(
new SignalMapping(
"PIN_A20", sw+
"[3]"));
269 switchMapping->push_back(
new SignalMapping(
"PIN_K19", sw+
"[4]"));
270 switchMapping->push_back(
new SignalMapping(
"PIN_J19", sw+
"[5]"));
271 switchMapping->push_back(
new SignalMapping(
"PIN_L19", sw+
"[6]"));
272 switchMapping->push_back(
new SignalMapping(
"PIN_L20", sw+
"[7]"));
277 SignalMappingList* pbMapping =
new SignalMappingList;
278 pbMapping->push_back(
new SignalMapping(
"PIN_B17", pb+
"[0]"));
279 pbMapping->push_back(
new SignalMapping(
"PIN_A17", pb+
"[1]"));
280 pbMapping->push_back(
new SignalMapping(
"PIN_A16", pb+
"[2]"));
281 pbMapping->push_back(
new SignalMapping(
"PIN_K17", pb+
"[3]"));
TTAMachine::Machine * machine
the architecture definition of the estimated processor
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
virtual size_t portCount() const
void addSignalMapping(const PlatInt::SignalMapping &mapping)
virtual void writeProjectFiles()=0
virtual ~Stratix3DevKitIntegrator()
virtual ProjectFileGenerator * projectFileGenerator() const
PlatInt::PinMap stratix3Pins_
virtual void integrateProcessor(const ProGe::NetlistBlock *ttaCore)
Stratix3DevKitIntegrator()
virtual void setDeviceFamily(TCEString devFamily)
static const TCEString DEVICE_FAMILY_
static const TCEString DEVICE_SPEED_CLASS_
virtual bool chopTaggedSignals() const
static const int DEFAULT_FREQ_
static const TCEString DEVICE_PACKAGE_
virtual void printInfo(std::ostream &stream) const
virtual TCEString deviceSpeedClass() const
virtual int targetClockFrequency() const
virtual TCEString devicePackage() const
QuartusProjectGenerator * quartusGen_
static const TCEString PIN_TAG_
static const TCEString DEVICE_NAME_
virtual TCEString deviceFamily() const
void addSignalMapping(const TCEString &signal)
virtual TCEString pinTag() const
std::vector< SignalMapping * > SignalMappingList
std::pair< TCEString, TCEString > SignalMapping
HDL
HDLs supported by ProGe.