OpenASIP 2.2
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Public Member Functions | Protected Member Functions | Private Member Functions | Private Attributes | Static Private Attributes | List of all members
Stratix3DevKitIntegrator Class Reference

#include <Stratix3DevKitIntegrator.hh>

Inheritance diagram for Stratix3DevKitIntegrator:
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Collaboration diagram for Stratix3DevKitIntegrator:
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Public Member Functions

 Stratix3DevKitIntegrator ()
 
 Stratix3DevKitIntegrator (const TTAMachine::Machine *machine, const IDF::MachineImplementation *idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString coreEntityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)
 
virtual ~Stratix3DevKitIntegrator ()
 
virtual void integrateProcessor (const ProGe::NetlistBlock *ttaCore)
 
virtual TCEString deviceFamily () const
 
virtual void setDeviceFamily (TCEString devFamily)
 
virtual TCEString devicePackage () const
 
virtual TCEString deviceSpeedClass () const
 
virtual int targetClockFrequency () const
 
virtual void printInfo (std::ostream &stream) const
 
- Public Member Functions inherited from AlteraIntegrator
 AlteraIntegrator ()
 
 AlteraIntegrator (const TTAMachine::Machine *machine, const IDF::MachineImplementation *idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString entityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)
 
virtual ~AlteraIntegrator ()
 
- Public Member Functions inherited from PlatformIntegrator
 PlatformIntegrator ()
 
 PlatformIntegrator (const TTAMachine::Machine *machine, const IDF::MachineImplementation *idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString coreEntityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)
 
virtual ~PlatformIntegrator ()
 
void setDeviceName (TCEString devName)
 
TCEString deviceName () const
 
const ProGe::NetlistBlockprogeBlock () const
 
const ProGe::NetlistBlocktoplevelBlock () const
 
void setSharedOutputDir (const TCEString &sharedDir)
 
TCEString outputPath () const
 
TCEString outputFilePath (TCEString fileName, bool absolute=false) const
 
TCEString coreEntityName () const
 
const TTAMachine::Machinemachine () const
 
const IDF::MachineImplementationidf () const
 
const MemInfoimemInfo () const
 
const MemInfodmemInfo (TTAMachine::AddressSpace *as) const
 
const MemInfodmemInfo (int index) const
 
int dmemCount () const
 
ProGe::NetlistPortclockPort () const
 
ProGe::NetlistPortresetPort () const
 

Protected Member Functions

virtual TCEString pinTag () const
 
virtual bool chopTaggedSignals () const
 
virtual ProjectFileGeneratorprojectFileGenerator () const
 
- Protected Member Functions inherited from AlteraIntegrator
virtual MemoryGeneratorimemInstance (MemInfo imem, int coreId)
 
virtual MemoryGeneratordmemInstance (MemInfo dmem, TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
 
- Protected Member Functions inherited from PlatformIntegrator
ProGe::NetlistBlockintegratorBlock ()
 
virtual void initPlatformNetlist (const ProGe::NetlistBlock *progeBlock)
 
virtual bool integrateCore (const ProGe::NetlistBlock &cores, int coreId)
 
virtual void exportUnconnectedPorts (int coreId)
 
virtual void connectToplevelPort (const ProGe::NetlistPort &corePort, const TCEString signalPrefix="")
 
virtual bool hasPinTag (const TCEString &signal) const
 
void copyProgeBlockToNetlist (const ProGe::NetlistBlock *progeBlock)
 
virtual bool createMemories (int coreId)
 
virtual bool generateMemory (MemoryGenerator &memGen, std::vector< TCEString > &generatedFiles, int memIndex, int coreId)
 
virtual void writeNewToplevel ()
 
void addProGeFiles () const
 
TCEString programName () const
 
TCEString progeFilePath (TCEString fileName, bool absolute=false) const
 
TCEString tbFilePath (TCEString fileName, bool absolute=false) const
 
TCEString chopSignalToTag (const TCEString &original, const TCEString &tag) const
 
void progeOutputHdlFiles (std::vector< TCEString > &files) const
 
std::ostream & warningStream () const
 
std::ostream & errorStream () const
 
TCEString platformEntityName () const
 
void parseDataMemories ()
 
void clearDataMemories ()
 
MemInfo readLsuParameters (const TTAMachine::FunctionUnit &lsu)
 

Private Member Functions

void generatePinMap ()
 
void mapToplevelPorts ()
 
void addSignalMapping (const TCEString &signal)
 

Private Attributes

QuartusProjectGeneratorquartusGen_
 
PlatInt::PinMap stratix3Pins_
 

Static Private Attributes

static const TCEString DEVICE_FAMILY_ = "Stratix III"
 
static const TCEString DEVICE_NAME_ = "EP3SL150F1152C2"
 
static const TCEString DEVICE_PACKAGE_ = "F1152"
 
static const TCEString DEVICE_SPEED_CLASS_ = "2"
 
static const TCEString PIN_TAG_ = "STRATIXIII"
 
static const int DEFAULT_FREQ_ = 125
 

Additional Inherited Members

- Static Protected Attributes inherited from PlatformIntegrator
static const TCEString TTA_CORE_CLK = "clk"
 
static const TCEString TTA_CORE_RSTX = "rstx"
 

Detailed Description

Definition at line 44 of file Stratix3DevKitIntegrator.hh.

Constructor & Destructor Documentation

◆ Stratix3DevKitIntegrator() [1/2]

Stratix3DevKitIntegrator::Stratix3DevKitIntegrator ( )

Definition at line 59 of file Stratix3DevKitIntegrator.cc.

59 :
61}
QuartusProjectGenerator * quartusGen_

◆ Stratix3DevKitIntegrator() [2/2]

Stratix3DevKitIntegrator::Stratix3DevKitIntegrator ( const TTAMachine::Machine machine,
const IDF::MachineImplementation idf,
ProGe::HDL  hdl,
TCEString  progeOutputDir,
TCEString  coreEntityName,
TCEString  outputDir,
TCEString  programName,
int  targetClockFreq,
std::ostream &  warningStream,
std::ostream &  errorStream,
const MemInfo imem,
MemType  dmemType 
)

Definition at line 64 of file Stratix3DevKitIntegrator.cc.

76 :
77 AlteraIntegrator(machine, idf, hdl, progeOutputDir, coreEntityName,
78 outputDir, programName, targetClockFreq, warningStream,
79 errorStream, imem, dmemType),
82}
const TTAMachine::Machine * machine() const
std::ostream & warningStream() const
const IDF::MachineImplementation * idf() const
TCEString programName() const
std::ostream & errorStream() const
void setDeviceName(TCEString devName)
TCEString coreEntityName() const
static const TCEString DEVICE_NAME_

References DEVICE_NAME_, and PlatformIntegrator::setDeviceName().

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◆ ~Stratix3DevKitIntegrator()

Stratix3DevKitIntegrator::~Stratix3DevKitIntegrator ( )
virtual

Definition at line 85 of file Stratix3DevKitIntegrator.cc.

85 {
86
87 for (PlatInt::PinMap::iterator iter = stratix3Pins_.begin();
88 iter != stratix3Pins_.end(); iter++) {
89 if (iter->second != NULL) {
90 for (unsigned int i = 0; i < iter->second->size(); i++) {
91 delete iter->second->at(i);
92 }
93 delete iter->second;
94 }
95 }
96 if (quartusGen_ != NULL) {
97 delete quartusGen_;
98 }
99}

References quartusGen_, and stratix3Pins_.

Member Function Documentation

◆ addSignalMapping()

void Stratix3DevKitIntegrator::addSignalMapping ( const TCEString signal)
private

Definition at line 221 of file Stratix3DevKitIntegrator.cc.

221 {
222
223 if (stratix3Pins_.find(signal) == stratix3Pins_.end()) {
224 warningStream() << "Warning: didn't find mapping for signal name "
225 << signal << endl;
226 return;
227 }
228
229 SignalMappingList* mappings = stratix3Pins_.find(signal)->second;
230 for (unsigned int i = 0; i < mappings->size(); i++) {
231 quartusGen_->addSignalMapping(*mappings->at(i));
232 }
233}
void addSignalMapping(const PlatInt::SignalMapping &mapping)
std::vector< SignalMapping * > SignalMappingList

References ProjectFileGenerator::addSignalMapping(), quartusGen_, stratix3Pins_, and PlatformIntegrator::warningStream().

Referenced by mapToplevelPorts().

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◆ chopTaggedSignals()

bool Stratix3DevKitIntegrator::chopTaggedSignals ( ) const
protectedvirtual

Implements PlatformIntegrator.

Definition at line 198 of file Stratix3DevKitIntegrator.cc.

198 {
199
200 return true;
201}

◆ deviceFamily()

TCEString Stratix3DevKitIntegrator::deviceFamily ( ) const
virtual

Returns the FPGA device family

Implements PlatformIntegrator.

Definition at line 127 of file Stratix3DevKitIntegrator.cc.

127 {
128
129 return DEVICE_FAMILY_;
130}
static const TCEString DEVICE_FAMILY_

References DEVICE_FAMILY_.

◆ devicePackage()

TCEString Stratix3DevKitIntegrator::devicePackage ( ) const
virtual

Returns the device package name

Implements PlatformIntegrator.

Definition at line 146 of file Stratix3DevKitIntegrator.cc.

146 {
147
148 return DEVICE_PACKAGE_;
149}
static const TCEString DEVICE_PACKAGE_

References DEVICE_PACKAGE_.

◆ deviceSpeedClass()

TCEString Stratix3DevKitIntegrator::deviceSpeedClass ( ) const
virtual

Returns the device speed class

Implements PlatformIntegrator.

Definition at line 153 of file Stratix3DevKitIntegrator.cc.

153 {
154
155 return DEVICE_SPEED_CLASS_;
156}
static const TCEString DEVICE_SPEED_CLASS_

References DEVICE_SPEED_CLASS_.

◆ generatePinMap()

void Stratix3DevKitIntegrator::generatePinMap ( )
private

Definition at line 237 of file Stratix3DevKitIntegrator.cc.

237 {
238
239 // clk
241 clk->push_back(new SignalMapping("PIN_B16","clk"));
242 stratix3Pins_["clk"] = clk;
243
244 // reset to push button CPU_RESET
246 rstx->push_back(new SignalMapping("PIN_AP5","rstx"));
247 stratix3Pins_["rstx"] = rstx;
248
249 // leds
250 const TCEString led = PIN_TAG_+"_LED";
251 SignalMappingList* ledMapping = new SignalMappingList;
252 ledMapping->push_back(new SignalMapping("PIN_F21", led+"[0]"));
253 ledMapping->push_back(new SignalMapping("PIN_C23", led+"[1]"));
254 ledMapping->push_back(new SignalMapping("PIN_B23", led+"[2]"));
255 ledMapping->push_back(new SignalMapping("PIN_A23", led+"[3]"));
256 ledMapping->push_back(new SignalMapping("PIN_D19", led+"[4]"));
257 ledMapping->push_back(new SignalMapping("PIN_C19", led+"[5]"));
258 ledMapping->push_back(new SignalMapping("PIN_F19", led+"[6]"));
259 ledMapping->push_back(new SignalMapping("PIN_E19", led+"[7]"));
260 stratix3Pins_[led] = ledMapping;
261
262 // dip switches
263 const TCEString sw = PIN_TAG_+"_USER_DIPSW";
264 SignalMappingList* switchMapping = new SignalMappingList;
265 switchMapping->push_back(new SignalMapping("PIN_B19", sw+"[0]"));
266 switchMapping->push_back(new SignalMapping("PIN_A19", sw+"[1]"));
267 switchMapping->push_back(new SignalMapping("PIN_C18", sw+"[2]"));
268 switchMapping->push_back(new SignalMapping("PIN_A20", sw+"[3]"));
269 switchMapping->push_back(new SignalMapping("PIN_K19", sw+"[4]"));
270 switchMapping->push_back(new SignalMapping("PIN_J19", sw+"[5]"));
271 switchMapping->push_back(new SignalMapping("PIN_L19", sw+"[6]"));
272 switchMapping->push_back(new SignalMapping("PIN_L20", sw+"[7]"));
273 stratix3Pins_[sw] = switchMapping;
274
275 // push buttons
276 const TCEString pb = PIN_TAG_+"_USER_PB";
277 SignalMappingList* pbMapping = new SignalMappingList;
278 pbMapping->push_back(new SignalMapping("PIN_B17", pb+"[0]"));
279 pbMapping->push_back(new SignalMapping("PIN_A17", pb+"[1]"));
280 pbMapping->push_back(new SignalMapping("PIN_A16", pb+"[2]"));
281 pbMapping->push_back(new SignalMapping("PIN_K17", pb+"[3]"));
282 stratix3Pins_[pb] = pbMapping;
283
284}
std::pair< TCEString, TCEString > SignalMapping

References PIN_TAG_, and stratix3Pins_.

Referenced by integrateProcessor().

◆ integrateProcessor()

void Stratix3DevKitIntegrator::integrateProcessor ( const ProGe::NetlistBlock progeBlock)
virtual

Integrates the TTA core(s) generated by ProGe

Parameters
progeBlockThe toplevel netlist block created by ProGe

Reimplemented from AlteraIntegrator.

Definition at line 103 of file Stratix3DevKitIntegrator.cc.

104 {
105
107
108 initPlatformNetlist(ttaCore);
109
110 const NetlistBlock& core = progeBlock();
111 int coreId = -1;
112 if (!integrateCore(core, coreId)) {
113 return;
114 }
115
117
119
121
123}
virtual void initPlatformNetlist(const ProGe::NetlistBlock *progeBlock)
virtual bool integrateCore(const ProGe::NetlistBlock &cores, int coreId)
const ProGe::NetlistBlock & progeBlock() const
virtual void writeNewToplevel()
virtual void writeProjectFiles()=0
virtual ProjectFileGenerator * projectFileGenerator() const

References PlatformIntegrator::addProGeFiles(), generatePinMap(), PlatformIntegrator::initPlatformNetlist(), PlatformIntegrator::integrateCore(), mapToplevelPorts(), PlatformIntegrator::progeBlock(), projectFileGenerator(), PlatformIntegrator::writeNewToplevel(), and ProjectFileGenerator::writeProjectFiles().

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◆ mapToplevelPorts()

void Stratix3DevKitIntegrator::mapToplevelPorts ( )
private

Definition at line 212 of file Stratix3DevKitIntegrator.cc.

212 {
214 for (size_t i = 0; i < tl.portCount(); i++) {
215 addSignalMapping(tl.port(i).name());
216 }
217}
ProGe::NetlistBlock * integratorBlock()
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
virtual size_t portCount() const
std::string name() const
void addSignalMapping(const TCEString &signal)

References addSignalMapping(), PlatformIntegrator::integratorBlock(), ProGe::NetlistPort::name(), ProGe::NetlistBlock::port(), and ProGe::NetlistBlock::portCount().

Referenced by integrateProcessor().

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◆ pinTag()

TCEString Stratix3DevKitIntegrator::pinTag ( ) const
protectedvirtual

Implements PlatformIntegrator.

Definition at line 191 of file Stratix3DevKitIntegrator.cc.

191 {
192
193 return PIN_TAG_;
194}

References PIN_TAG_.

◆ printInfo()

void Stratix3DevKitIntegrator::printInfo ( std::ostream &  stream) const
virtual

Prints information about the platform

Implements PlatformIntegrator.

Definition at line 172 of file Stratix3DevKitIntegrator.cc.

172 {
173
174 stream
175 << "Integrator name: Stratix3DevKit" << std::endl
176 << "---------------------------------" << std::endl
177 << "Integrates TTA core to Altera Stratix III Development Kit"
178 << std::endl << "with" << DEVICE_NAME_ << " device." << std::endl
179 << "Creates project files for QuartusII v8.0 program." << std::endl
180 << "Supported instruction memory types are 'onchip' and 'vhdl_array."
181 << std::endl
182 << "Supported data memory type is 'onchip'."
183 << std::endl
184 << "Default clock frequency is 125 MHz." << std::endl
185 << "Active low reset is connected to CPU RESET button."
186 << std::endl << std::endl;
187}

References DEVICE_NAME_.

◆ projectFileGenerator()

ProjectFileGenerator * Stratix3DevKitIntegrator::projectFileGenerator ( ) const
protectedvirtual

Implements PlatformIntegrator.

Definition at line 205 of file Stratix3DevKitIntegrator.cc.

205 {
206
207 return quartusGen_;
208}

References quartusGen_.

Referenced by integrateProcessor().

◆ setDeviceFamily()

void Stratix3DevKitIntegrator::setDeviceFamily ( TCEString  devFamily)
virtual

Set the FPGA device family.

Intended for TTA IP integration. Integrator can device whether this overrides the default device family.

Implements PlatformIntegrator.

Definition at line 134 of file Stratix3DevKitIntegrator.cc.

134 {
135
136 if (devFamily != DEVICE_FAMILY_) {
138 << "Warning: Refusing to change device family!" << endl
139 << "- Original device family: " << DEVICE_FAMILY_ << endl
140 << "- New device family: " << devFamily << endl;
141 }
142}

References DEVICE_FAMILY_, and PlatformIntegrator::warningStream().

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◆ targetClockFrequency()

int Stratix3DevKitIntegrator::targetClockFrequency ( ) const
virtual

Returns the target clock frequency in MHz

Reimplemented from PlatformIntegrator.

Definition at line 160 of file Stratix3DevKitIntegrator.cc.

160 {
161
162 int freq = DEFAULT_FREQ_;
163
166 }
167 return freq;
168}
virtual int targetClockFrequency() const

References DEFAULT_FREQ_, and PlatformIntegrator::targetClockFrequency().

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Member Data Documentation

◆ DEFAULT_FREQ_

const int Stratix3DevKitIntegrator::DEFAULT_FREQ_ = 125
staticprivate

Definition at line 109 of file Stratix3DevKitIntegrator.hh.

Referenced by targetClockFrequency().

◆ DEVICE_FAMILY_

const TCEString Stratix3DevKitIntegrator::DEVICE_FAMILY_ = "Stratix III"
staticprivate

Definition at line 99 of file Stratix3DevKitIntegrator.hh.

Referenced by deviceFamily(), and setDeviceFamily().

◆ DEVICE_NAME_

const TCEString Stratix3DevKitIntegrator::DEVICE_NAME_ = "EP3SL150F1152C2"
staticprivate

Definition at line 101 of file Stratix3DevKitIntegrator.hh.

Referenced by printInfo(), and Stratix3DevKitIntegrator().

◆ DEVICE_PACKAGE_

const TCEString Stratix3DevKitIntegrator::DEVICE_PACKAGE_ = "F1152"
staticprivate

Definition at line 103 of file Stratix3DevKitIntegrator.hh.

Referenced by devicePackage().

◆ DEVICE_SPEED_CLASS_

const TCEString Stratix3DevKitIntegrator::DEVICE_SPEED_CLASS_ = "2"
staticprivate

Definition at line 105 of file Stratix3DevKitIntegrator.hh.

Referenced by deviceSpeedClass().

◆ PIN_TAG_

const TCEString Stratix3DevKitIntegrator::PIN_TAG_ = "STRATIXIII"
staticprivate

Definition at line 107 of file Stratix3DevKitIntegrator.hh.

Referenced by generatePinMap(), and pinTag().

◆ quartusGen_

QuartusProjectGenerator* Stratix3DevKitIntegrator::quartusGen_
private

◆ stratix3Pins_

PlatInt::PinMap Stratix3DevKitIntegrator::stratix3Pins_
private

The documentation for this class was generated from the following files: