AlteraIntegrator.cc

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/*
    Copyright (c) 2002-2010 Tampere University.
 
    This file is part of TTA-Based Codesign Environment (TCE).
 
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/**
 * @file AlteraIntegrator.cc
 *
 * Implementation of AlteraIntegrator class.
 *
 * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
 * @note rating: red
 */
 
#include "AlteraIntegrator.hh"
#include "AlteraOnchipRamGenerator.hh"
#include "AlteraOnchipRomGenerator.hh"
#include "VhdlRomGenerator.hh"
#include "ProjectFileGenerator.hh"
#include "Machine.hh"
#include "NetlistPort.hh"
#include "NetlistBlock.hh"
using ProGe::NetlistBlock;
using ProGe::NetlistPort;
 
AlteraIntegrator::AlteraIntegrator(): PlatformIntegrator() {
}
 
 
AlteraIntegrator::AlteraIntegrator(
    const TTAMachine::Machine* machine,
    const IDF::MachineImplementation* idf,
    ProGe::HDL hdl,
    TCEString progeOutputDir,
    TCEString coreEntityName,
    TCEString outputDir,
    TCEString programName,
    int targetClockFreq,
    std::ostream& warningStream,
    std::ostream& errorStream,
    const MemInfo& imem,
    MemType dmemType):
    PlatformIntegrator(machine, idf, hdl, progeOutputDir, coreEntityName,
                       outputDir, programName, targetClockFreq, warningStream,
                       errorStream, imem, dmemType),
    imemGen_(NULL), dmemGen_() {
}
 
 
AlteraIntegrator::~AlteraIntegrator() {
 
    if (imemGen_ != NULL) {
        delete imemGen_;
    }
    if (!dmemGen_.empty()) {
        std::map<TCEString, MemoryGenerator*>::iterator iter =
            dmemGen_.begin();
        while (iter != dmemGen_.end()) {
            delete iter->second;
            iter++;
        }
    }
}
 
 
void
AlteraIntegrator::integrateProcessor(
    const ProGe::NetlistBlock* progeBlockInOldNetlist) {
 
    initPlatformNetlist(progeBlockInOldNetlist);
 
    const NetlistBlock& core = progeBlock();
    int coreId = -1;
    if (!integrateCore(core, coreId)) {
        return;
    }
 
    writeNewToplevel();
    
    addProGeFiles();
 
    projectFileGenerator()->writeProjectFiles();
}
 
MemoryGenerator&
AlteraIntegrator::imemInstance(MemInfo imem, int coreId) {
    assert(imem.type != UNKNOWN && "Imem type not set!");
 
    TCEString initFile;
    if (imem.type == ONCHIP) {
        initFile = programName() + ".mif";
        projectFileGenerator()->addMemInitFile(initFile);
    } else if (imem.type == VHDL_ARRAY) {
        initFile = programName() + "_imem_pkg.vhdl";
    }
 
    if (imemGen_ == NULL) {
        if (imem.type == ONCHIP) {
            imemGen_ = 
                new AlteraOnchipRomGenerator(
                    imem.mauWidth, imem.widthInMaus, imem.portAddrw, initFile,
                    this, warningStream(), errorStream());
        } else if (imem.type == VHDL_ARRAY) {
            imemGen_ = new VhdlRomGenerator(
                imem.mauWidth, imem.widthInMaus, imem.portAddrw, initFile,
                this, warningStream(), errorStream());
        } else {
            TCEString msg = "Unsupported instruction memory type";
            throw InvalidData(__FILE__, __LINE__, "AlteraIntegrator", msg);
        }
    }
    return *imemGen_;
}
 
MemoryGenerator&
AlteraIntegrator::dmemInstance(
    MemInfo dmem, TTAMachine::FunctionUnit& lsuArch,
    std::vector<std::string> lsuPorts) {
    MemoryGenerator* memGen = NULL;
    if (dmemGen_.find(dmem.asName) != dmemGen_.end()) {
        memGen = dmemGen_.find(dmem.asName)->second;
    } else {
        if (dmem.type == ONCHIP) {
            TCEString initFile = programName() + "_" + dmem.asName + ".mif";
            // onchip mem size is scalable, use value from adf's Address Space
            int addrw = dmem.portAddrw;
            memGen =
                new AlteraOnchipRamGenerator(
                    dmem.mauWidth, dmem.widthInMaus, addrw, initFile,
                    this, warningStream(), errorStream());
            projectFileGenerator()->addMemInitFile(initFile); 
        } else {
            TCEString msg = "Unsupported data memory type";
            throw InvalidData(__FILE__, __LINE__, "AlteraIntegrator", msg);
        }
        memGen->addLsu(lsuArch, lsuPorts);
        dmemGen_[dmem.asName] = memGen;
    }
    return *memGen;
}