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67 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
68 std::cerr <<
"\tPerforming BFSchduleBU for: " <<
mn_.
toString() <<
69 " lc limit: " <<
lc_ << std::endl;
118 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
119 std::cerr <<
"\t\tForced bypass failed" << std::endl;
140 if (prefCycle != INT_MAX) {
166 if (!copyFUs.empty()) {
167 regCopy = regCopyBefore =
180 regCopy = regCopyBefore =
187 regCopy = regCopyBefore =
199 int ddglc = std::min(
lc_,
ddg().latestCycle(
mn_,
ii(),
false,
true));
203 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
204 std::cerr <<
"\t\tddg lc: " << ddglc << std::endl;
205 std::cerr <<
"\t\tddg ec: " << ddgec << std::endl;
208 int latestIfRenamed =
210 ddg().latestCycle(
mn_,
ii(),
true,
false));
213 latestIfRenamed =
rmLC(latestIfRenamed,
mn_);
214 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
215 std::cerr <<
"\t\tRenaming could benefit move: " <<
mn_.
toString() <<
216 " lc: " << ddglc <<
" renamed lc: " << latestIfRenamed
224 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
225 std::cerr <<
"\t\tPushed antidep dests down, new lc: "
226 << ddglc << std::endl;
229 latestIfRenamed = std::min(
lc_,
231 mn_,
ii(),
true,
false));
232 latestIfRenamed =
rmLC(latestIfRenamed,
mn_);
234 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
237 std::cerr <<
"\t\tCould not push antidep dests down" << std::endl;
242 if (latestIfRenamed > ddglc &&
245 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
246 std::cerr <<
"Antideps still limit scheduling of: "
247 <<
mn_.
toString() <<
" even after pushing? them down!"
257 int renamedRMLC =
rmLC(renamedDDGLC,
mn_);
258 if (renamedRMLC <= rmlc) {
259 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
260 std::cerr <<
"\t\tRenaming did not help rmlc, undoing"
266 ddglc = renamedDDGLC;
268 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
269 std::cerr <<
"\t\tRenamed Source Reg, new lc: "
270 << ddglc << std::endl;
277 if ((ddglc < ddgec || rmlc < ddgec) && ddglc >=0 &&
ii()) {
278 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
279 std::cerr <<
"\t\tPushing up deps could benefit move: "
281 <<
" ec: " << ddgec << std::endl;
285 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
286 std::cerr <<
"pushed antidep something up, ec now: "
287 << ddgec << std::endl;
297 ddg().latestCycle(
mn_,
ii(),
false,
false,
true));
298 if (latestNoGuard > ddglc) {
302 ddglc = std::min(
lc_,
303 ddg().latestCycle(
mn_,
ii(),
false,
false));
304 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
305 std::cerr <<
"\t\tRemoved guards from dests, new lc: "
306 << ddglc << std::endl;
309 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
310 std::cerr <<
"\t\tCould not remove guards from dests"
318 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
319 std::cerr <<
"\t\tbfschdbu: rmlc: " << rmlc << std::endl;
322 if (rmlc < ddgec &&
ii() != 0) {
323 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
324 std::cerr <<
"\t\t\tDDG ec " << ddgec <<
" on loop(II:"
327 if (
ddg().earliestCycle(
mn_, INT_MAX/2,
false,
false) < rmlc) {
328 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
329 std::cerr <<
"Limiter is a loop edge" << std::endl;
330 std::cerr <<
"\t\t\t\tddgec was: " << ddgec <<
" ddglc was: "
331 << ddgec <<
" rmlc was: " << rmlc << std::endl;
335 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
336 std::cerr <<
"Pushed loop deps up." << std::endl;
338 ddglc = std::min(
lc_,
ddg().latestCycle(
mn_,
ii(),
false,
false));
341 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
342 std::cerr <<
"\t\t\t\tddgec now: " << ddgec <<
"ddglc now: "
343 << ddgec <<
"rmlc now: " << rmlc << std::endl;
347 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
348 std::cerr <<
"loop dep psuh failed." << std::endl;
351 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
353 std::cerr <<
"Limiter not a loop edge." << std::endl;
358 if (rmlc >= ddgec && rmlc != INT_MAX) {
360 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
361 std::cerr <<
"\t\tassigning to: " << rmlc << std::endl;
365 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
369 if (regCopyBefore != NULL) {
398 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
399 std::cerr <<
"\t\tUndoing BU schedule of: " <<
mn_.
toString() <<std::endl;
403 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
404 std::cerr <<
"\t\t\tunassigning here." << std::endl;
413 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
415 std::cerr <<
"\t\t\tbypasser scheduled this, no need to undo here"
virtual bool isFUPort() const
virtual void unassign(MoveNode &mn, bool disposePrologCopy=true)
virtual bool isTriggering() const
void undoAndRemovePreChildren()
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
bool isDestinationVariable() const
virtual TCEString name() const
std::string toString() const
virtual const TTAMachine::RegisterFile & registerFile() const
const TTAMachine::RegisterFile * RFReadPortCountPreventsScheduling(const MoveNode &mn)
bool isDestinationOperation() const
TTAMachine::Bus & universalBus() const
BFScheduleBU(BF2Scheduler &sched, MoveNode &mn, int lc, bool allowEarlyBypass, bool allowLateBypass, bool allowEarlySharing)
Terminal & destination() const
static UniversalMachine & instance()
const TTAMachine::Bus & bus() const
std::stack< Reversible * > preChildren_
const TTAMachine::Machine & targetMachine() const
#define assert(condition)
bool isControlFlowMove() const
static bool isSourceUniversalReg(const MoveNode &mn)
virtual bool isGPR() const
bool isSourceOperation() const
DataDependenceGraph & ddg()
bool canBeScheduled(const MoveNode &mn)
static int prefResultCycle(const MoveNode &mn)
virtual void writeToDotFile(const TCEString &fileName) const
int earliestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegWaRs=false, bool ignoreRegWaWs=false, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false, bool assumeBypassing=false) const
bool isSourceVariable() const
ProgramOperation & destinationOperation(unsigned int index=0) const
TTAProgram::Move & move()
virtual int rmLC(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1)
bool runPreChild(Reversible *preChild)
virtual bool operator()()
bool runPostChild(Reversible *preChild)
virtual int width() const
static FUSet copyOpFUs(const TTAMachine::Machine &mach, const MoveNode &mn)
void setBus(const TTAMachine::Bus &bus)