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ProGe::NetlistGenerator Class Reference

#include <NetlistGenerator.hh>

Collaboration diagram for ProGe::NetlistGenerator:
Collaboration graph

Public Member Functions

 NetlistGenerator (const ProGeContext &context, ICDecoderGeneratorPlugin &plugin)
 
virtual ~NetlistGenerator ()
 
NetlistBlock * generate (const ProGeOptions &options, int imemWidthInMAUs, TCEString entityNameStr, std::ostream &warningStream)
 
NetlistPort & netlistPort (const TTAMachine::Port &port, Direction dir=IN) const
 
NetlistBlock & netlistBlock (const TTAMachine::Unit &unit) const
 
NetlistPort & loadPort (const NetlistPort &port) const
 
bool hasOpcodePort (const NetlistPort &port) const
 
NetlistPort & rfOpcodePort (const NetlistPort &port) const
 
NetlistPort & rfGuardPort (const NetlistBlock &rfBlock) const
 
NetlistPort & fuOpcodePort (const NetlistBlock &fuBlock) const
 
NetlistPort & fuGuardPort (const NetlistPort &fuPort) const
 
NetlistPort & clkPort (const NetlistBlock &block) const
 
NetlistPort & rstPort (const NetlistBlock &block) const
 
bool hasGlockPort (const NetlistBlock &block) const
 
NetlistPort & glockPort (const NetlistBlock &block) const
 
bool hasGlockReqPort (const NetlistBlock &block) const
 
NetlistPort & glockReqPort (const NetlistBlock &block) const
 
NetlistPort & immediateUnitWritePort (const TTAMachine::ImmediateUnit &iu) const
 
NetlistPort & gcuReturnAddressInPort () const
 
NetlistPort & gcuReturnAddressOutPort () const
 
NetlistBlock & ttaCore () const
 
NetlistBlock & instructionDecoder () const
 
NetlistBlock & instructionDecompressor () const
 
NetlistBlock & instructionFetch () const
 
HDB::FUEntry & fuEntry (const std::string &fuName) const
 
HDB::RFEntry & rfEntry (const std::string &rfName) const
 
const ProGeContext & context () const
 
void mapGlobalLockRequestPort (const NetlistBlock &block, NetlistPort &glockReqPort)
 

Static Public Attributes

static const std::string DECODER_INSTR_WORD_PORT
 Instruction word port name in instruction decoder. More...
 
static const std::string DECODER_RESET_PORT = RESET_PORT_NAME
 Reset port name in instruction decoder. More...
 
static const std::string DECODER_CLOCK_PORT = CLOCK_PORT_NAME
 Clock port name in instruction decoder. More...
 
static const std::string DECODER_RA_LOAD_PORT
 RA load port name in instruction decoder. More...
 
static const std::string DECODER_PC_LOAD_PORT
 PC load port name in instruction decoder. More...
 
static const std::string DECODER_PC_OPCODE_PORT
 PC opcode port name in instruction decoder. More...
 
static const std::string DECODER_LOCK_REQ_OUT_PORT
 Lock request out port name in instruction decoder. More...
 
static const std::string DECODER_LOCK_REQ_IN_PORT
 Lock request in port name in instruction decoder. More...
 
static const std::string DECODER_LOCK_STATUS_PORT
 
static const std::string DECOMP_LOCK_REQ_IN_PORT
 Lock request in port name in decompressor. More...
 
static const std::string DECOMP_GLOCK_PORT
 Global lock out port name in decompressor. More...
 
static const std::string DECOMP_INSTR_WORD_PORT
 Instruction word port name in decompressor. More...
 
static const std::string ADDR_WIDTH
 
static const std::string FETCHBLOCK_PORT_NAME = "fetchblock"
 

Private Types

typedef std::multimap< const TTAMachine::Port *, NetlistPort * > PortCorrespondenceMap
 Multimap type to map ADF ports to NetlistPorts. More...
 
typedef std::map< const TTAMachine::Unit *, NetlistBlock * > UnitCorrespondenceMap
 Map type to map ADF Units to NetlistBlocks. More...
 
typedef std::map< const NetlistPort *, NetlistPort * > PortRelationMap
 Map type for NetlistPorts. More...
 
typedef std::map< const NetlistBlock *, NetlistPort * > PortPurposeMap
 Map type for NetlistPorts. More...
 
typedef std::map< const TTAMachine::ImmediateUnit *, NetlistPort * > IUPortMap
 Map type for port of immediate units. More...
 
typedef std::map< std::string, HDB::FUEntry * > FUEntryMap
 Map type for FUImplementation. More...
 
typedef std::map< std::string, HDB::RFEntry * > RFEntryMap
 Map type for RFImplementation. More...
 

Private Member Functions

void addGCUToNetlist (NetlistBlock &toplevelBlock, int imemWidthInMAUs)
 
void addFUToNetlist (const IDF::FUImplementationLocation &location, NetlistBlock &netlistBlock, std::ostream &warningStream)
 
GeneratableFUNetlistBlock * addGeneratableFUsToNetlist (const IDF::FUGenerated &fug, NetlistBlock &netlistBlock)
 
void addFUExternalPortsToNetlist (const HDB::FUImplementation &fuImplementation, NetlistBlock &coreBlock, NetlistBlock &fuBlock, const TTAMachine::FunctionUnit &adfFU)
 
void addRFToNetlist (const ProGeOptions &options, const IDF::RFImplementationLocation &location, NetlistBlock &netlistBlock)
 
void addIUToNetlist (const ProGeOptions &options, const IDF::RFImplementationLocation &location, NetlistBlock &netlistBlock)
 
void addBaseRFToNetlist (const ProGeOptions &options, const TTAMachine::BaseRegisterFile &regFile, const IDF::RFImplementationLocation &location, NetlistBlock &netlistBlock, const std::string &blockNamePrefix)
 
void mapNetlistPort (const TTAMachine::Port &adfPort, NetlistPort &netlistPort)
 
void mapNetlistBlock (const TTAMachine::Unit &unit, NetlistBlock &netlistBlock)
 
bool netlistPortIsMapped (const TTAMachine::Port &adfPort)
 
void mapLoadPort (const NetlistPort &port, NetlistPort &loadPort)
 
void mapRFOpcodePort (const NetlistPort &port, NetlistPort &opcodePort)
 
void mapClockPort (const NetlistBlock &block, NetlistPort &clkPort)
 
void mapResetPort (const NetlistBlock &block, NetlistPort &resetPort)
 
void mapGlobalLockPort (const NetlistBlock &block, NetlistPort &glockPort)
 
void mapRFGuardPort (const NetlistBlock &block, NetlistPort &guardPort)
 
void mapFUGuardPort (const NetlistPort &dataPort, NetlistPort &guardPort)
 
void mapFUOpcodePort (const NetlistBlock &block, NetlistPort &opcodePort)
 
void mapImmediateUnitWritePort (const TTAMachine::ImmediateUnit &iu, NetlistPort &port)
 
bool isParameterizable (const std::string &paramName, const HDB::FUEntry *fuEntry) const
 
unsigned int calculateAddressWidth (TTAMachine::FunctionUnit const *fu) const
 
TCEString checkInstanceName (const TCEString &baseInstanceName, const TCEString &moduleName) const
 
bool isLSU (const TTAMachine::FunctionUnit &fu) const
 

Static Private Member Functions

static bool isLSUDataPort (const TTAMachine::FunctionUnit &adfFU, const std::string &portName)
 
static Signal inferLSUSignal (const std::string &portName)
 
static int opcodePortWidth (const HDB::FUEntry &fu, std::ostream &warningStream)
 
static int opcodePortWidth (const TTAMachine::ControlUnit &gcu)
 
static TTAMachine::FUPort & findCorrespondingPort (const TTAMachine::FunctionUnit &fuToSearch, const TTAMachine::FunctionUnit &origFU, const std::string &portName)
 
static int instructionMemoryAddressWidth (const TTAMachine::Machine &machine)
 
static int instructionMemoryWidth (const TTAMachine::Machine &machine)
 
static TTAMachine::AddressSpace & instructionMemory (const TTAMachine::Machine &machine)
 
static Direction translateDirection (HDB::Direction direction)
 

Private Attributes

const ProGeContext & context_
 
ICDecoderGeneratorPlugin & plugin_
 The generator plugin. More...
 
PortCorrespondenceMap portCorrespondenceMap_
 Maps the ADF ports to the netlist ports. More...
 
UnitCorrespondenceMap unitCorrespondenceMap_
 Maps the ADF units to the netlist blocks. More...
 
PortRelationMap loadPortMap_
 Maps loads ports. More...
 
PortRelationMap rfOpcodePortMap_
 Maps opcode ports. More...
 
PortPurposeMap clkPorts_
 Maps clock ports. More...
 
PortPurposeMap rstPorts_
 Maps reset ports. More...
 
PortPurposeMap rfGuardPorts_
 Maps RF guard ports. More...
 
PortPurposeMap glockPorts_
 Maps global lock ports. More...
 
PortPurposeMap glockReqPorts_
 Maps global lock request ports. More...
 
PortRelationMap fuGuardPortMap_
 Maps FU guard ports. More...
 
PortPurposeMap fuOpcodePorts_
 Maps FU opcode ports. More...
 
IUPortMap iuPortMap_
 Maps the created netlist ports to immediate units. More...
 
NetlistBlock * coreBlock_
 The TTA core block. More...
 
NetlistBlock * instructionDecoder_
 The instruction decoder block. More...
 
NetlistBlock * instructionDecompressor_
 The instruction decompressor block. More...
 
NetlistBlock * instructionFetch_
 The instruction fetch block. More...
 
FUEntryMap fuEntryMap_
 Maps FU implementations for different FU's. More...
 
RFEntryMap rfEntryMap_
 Maps RF implementations for different RF's. More...
 
NetlistPort * raInPort_
 Return address in port in GCU (ifetch). More...
 
NetlistPort * raOutPort_
 Returns address out port in GCU (ifetch). More...
 

Friends

class GeneratableFUNetlistBlock
 

Detailed Description

Generates a netlist of processor building blocks. [DEPRECATED]

Definition at line 84 of file NetlistGenerator.hh.

Member Typedef Documentation

◆ FUEntryMap

typedef std::map<std::string, HDB::FUEntry*> ProGe::NetlistGenerator::FUEntryMap
private

Map type for FUImplementation.

Definition at line 174 of file NetlistGenerator.hh.

◆ IUPortMap

typedef std::map<const TTAMachine::ImmediateUnit*, NetlistPort*> ProGe::NetlistGenerator::IUPortMap
private

Map type for port of immediate units.

Definition at line 172 of file NetlistGenerator.hh.

◆ PortCorrespondenceMap

typedef std::multimap<const TTAMachine::Port*, NetlistPort*> ProGe::NetlistGenerator::PortCorrespondenceMap
private

Multimap type to map ADF ports to NetlistPorts.

Definition at line 162 of file NetlistGenerator.hh.

◆ PortPurposeMap

typedef std::map<const NetlistBlock*, NetlistPort*> ProGe::NetlistGenerator::PortPurposeMap
private

Map type for NetlistPorts.

Definition at line 169 of file NetlistGenerator.hh.

◆ PortRelationMap

typedef std::map<const NetlistPort*, NetlistPort*> ProGe::NetlistGenerator::PortRelationMap
private

Map type for NetlistPorts.

Definition at line 167 of file NetlistGenerator.hh.

◆ RFEntryMap

typedef std::map<std::string, HDB::RFEntry*> ProGe::NetlistGenerator::RFEntryMap
private

Map type for RFImplementation.

Definition at line 176 of file NetlistGenerator.hh.

◆ UnitCorrespondenceMap

typedef std::map<const TTAMachine::Unit*, NetlistBlock*> ProGe::NetlistGenerator::UnitCorrespondenceMap
private

Map type to map ADF Units to NetlistBlocks.

Definition at line 165 of file NetlistGenerator.hh.

Constructor & Destructor Documentation

◆ NetlistGenerator()

ProGe::NetlistGenerator::NetlistGenerator ( const ProGeContext &  context,
ICDecoderGeneratorPlugin &  plugin 
)

Definition at line 159 of file NetlistGenerator.cc.

161  : context_(context), plugin_(plugin), coreBlock_(NULL),
162  instructionDecoder_(NULL), instructionDecompressor_(NULL),
163  instructionFetch_(NULL), raInPort_(NULL), raOutPort_(NULL) {}

◆ ~NetlistGenerator()

ProGe::NetlistGenerator::~NetlistGenerator ( )
virtual

The destructor.

Definition at line 168 of file NetlistGenerator.cc.

168  {
169  MapTools::deleteAllValues(fuEntryMap_);
170  MapTools::deleteAllValues(rfEntryMap_);
171  }

References MapTools::deleteAllValues(), fuEntryMap_, and rfEntryMap_.

Here is the call graph for this function:

Member Function Documentation

◆ addBaseRFToNetlist()

void ProGe::NetlistGenerator::addBaseRFToNetlist ( const ProGeOptions &  options,
const TTAMachine::BaseRegisterFile &  regFile,
const IDF::RFImplementationLocation &  location,
NetlistBlock &  targetBlock,
const std::string &  blockNamePrefix 
)
private

Adds the RF or IU identified by the given RFImplementationLocation instance to the netlist.

Parameters
regFileThe corresponding RF (or IU) in ADF.
locationThe RFImplementationLocation instance.
netlistThe netlist.
blockNamePrefixPrefix to be added to the block name.
Exceptions
IOExceptionIf the HDB that contains the implementation cannot be accessed.
InvalidDataIf the RF entry in HDB does not have an implementation or architecture or if the HDB does not have the entry defined in the RFImplementationLocation instance at all.

Definition at line 1351 of file NetlistGenerator.cc.

1355  {
1356  RFEntry* entry = NULL;
1357  try {
1358  HDBManager& manager =
1359  HDBRegistry::instance().hdb(location.hdbFile());
1360  entry = manager.rfByEntryID(location.id());
1361  } catch (const KeyNotFound& e) {
1362  throw InvalidData(__FILE__, __LINE__, __func__, e.errorMessage());
1363  }
1364 
1365  if (!entry->hasImplementation() || !entry->hasArchitecture()) {
1366  format text("RF entry %1% does not have an implementation or "
1367  "architecture "
1368  "defined in HDB %2%.");
1369  text % location.id() % location.hdbFile();
1370  throw InvalidData(__FILE__, __LINE__, __func__, text.str());
1371  }
1372 
1373  rfEntryMap_.insert(std::make_pair(location.unitName(), entry));
1374  RFImplementation& implementation = entry->implementation();
1375  RFArchitecture& architecture = entry->architecture();
1376  TCEString instanceName = blockNamePrefix + location.unitName();
1377  TCEString moduleName = implementation.moduleName();
1378  instanceName = checkInstanceName(instanceName, moduleName);
1379  NetlistBlock* block = new NetlistBlock(moduleName, instanceName);
1380  targetBlock.addSubBlock(block);
1381  mapNetlistBlock(regFile, *block);
1382 
1383  // Add parameters (generics) to the block.
1384  for (int i = 0; i < implementation.parameterCount(); i++) {
1385  RFImplementation::Parameter param = implementation.parameter(i);
1386 
1387  // Check if parameter matches size or width parameter reference
1388  // and set/override its parameter value according to
1389  // architecture.
1390  if (param.name == implementation.sizeParameter()) {
1391  block->setParameter(implementation.sizeParameter(), "integer",
1392  Conversion::toString(regFile.numberOfRegisters()));
1393  } else if (param.name == implementation.widthParameter()) {
1394  block->setParameter(implementation.widthParameter(), "integer",
1395  Conversion::toString(regFile.width()));
1396  } else if (param.value == "") {
1397  format errorMsg(
1398  "Unable to resolve the value of parameter %1% of RF "
1399  "entry %2%.");
1400  errorMsg % param.name % location.id();
1401  throw InvalidData(__FILE__, __LINE__, __func__, errorMsg.str());
1402  } else {
1403  block->setParameter(param.name, param.type, param.value);
1404  }
1405  }
1406 
1407  // add ports
1408  for (int i = 0; i < implementation.portCount(); i++) {
1409  RFPortImplementation& port = implementation.port(i);
1410  NetlistPort* newInputPort = NULL;
1411  NetlistPort* newOutputPort = NULL;
1412  if (!implementation.widthParameter().empty()) {
1413  switch (port.direction()) {
1414  case HDB::BIDIR:
1415  newInputPort = new NetlistPort(port.name()+"_in",
1416  implementation.widthParameter(), regFile.width(),
1417  BIT_VECTOR, IN, *block);
1418  newOutputPort = new NetlistPort(port.name()+"_out",
1419  implementation.widthParameter(), regFile.width(),
1420  BIT_VECTOR, OUT, *block);
1421  break;
1422  case HDB::IN:
1423  newInputPort = new NetlistPort(port.name(),
1424  implementation.widthParameter(), regFile.width(),
1425  BIT_VECTOR, IN,
1426  *block);
1427  break;
1428  case HDB::OUT:
1429  newOutputPort = new NetlistPort(port.name(),
1430  implementation.widthParameter(), regFile.width(),
1431  BIT_VECTOR, OUT, *block);
1432  break;
1433  }
1434  } else {
1435  switch (port.direction()) {
1436  case HDB::BIDIR:
1437  newInputPort = new NetlistPort(port.name(),
1438  Conversion::toString(architecture.width()),
1439  BIT_VECTOR, IN, *block);
1440  newOutputPort = new NetlistPort(port.name(),
1441  Conversion::toString(architecture.width()),
1442  BIT_VECTOR, OUT, *block);
1443  break;
1444  case HDB::IN:
1445  newInputPort = new NetlistPort(port.name(),
1446  Conversion::toString(architecture.width()),
1447  BIT_VECTOR, IN, *block);
1448  break;
1449  case HDB::OUT:
1450  newOutputPort = new NetlistPort(port.name(),
1451  Conversion::toString(architecture.width()),
1452  BIT_VECTOR, OUT, *block);
1453  break;
1454  }
1455  }
1456  assert(newInputPort || newOutputPort);
1457 
1458  RFPort* rfPort = NULL;
1459  // map the port if it is not input port of IU (not visible in
1460  // ADF)
1461  if (dynamic_cast<const ImmediateUnit*>(&regFile) == NULL ||
1462  port.direction() != HDB::IN) {
1463 
1464  bool mapped = false;
1465  for (int i = 0; i < regFile.portCount(); i++) {
1466  rfPort = regFile.port(i);
1467  if (portCorrespondenceMap_.count(rfPort) == 0) {
1468  if ((port.direction() == HDB::IN &&
1469  rfPort->inputSocket() != NULL &&
1470  rfPort->outputSocket() == NULL) ||
1471  (port.direction() == HDB::OUT &&
1472  rfPort->outputSocket() != NULL &&
1473  rfPort->inputSocket() == NULL) ||
1474  (port.direction() == HDB::BIDIR &&
1475  rfPort->outputSocket() != NULL &&
1476  rfPort->inputSocket() != NULL)) {
1477  mapped = true;
1478  break;
1479  }
1480  }
1481  }
1482 
1483  if (!mapped) {
1484  format text("Unable to map port '%1%' of RF entry '%2%' in "
1485  "HDB '%3%' "
1486  "to any port in %4% '%5%'.");
1487  text % port.name() % location.id() % location.hdbFile();
1488  if (dynamic_cast<const ImmediateUnit*>(&regFile) != NULL) {
1489  text % "immediate unit";
1490  } else {
1491  text % "register file";
1492  }
1493  text % regFile.name();
1494  throw InvalidData(__FILE__, __LINE__, __func__, text.str());
1495  }
1496  }
1497 
1498  // if the given BaseRegisterFile is ImmediateUnit, keep track of
1499  // the
1500  // data ports that does not appear in ADF
1501  const ImmediateUnit* iu =
1502  dynamic_cast<const ImmediateUnit*>(&regFile);
1503  if (iu != NULL && newInputPort) {
1504  mapImmediateUnitWritePort(*iu, *newInputPort);
1505  }
1506 
1507  // add load port
1508  NetlistPort* loadPort =
1509  new NetlistPort(port.loadPort(), "1", BIT, IN, *block);
1510 
1511 
1512  // Map data (unless it is IU's write port) and load port
1513  if (rfPort != NULL) {
1514  if (newInputPort)
1515  mapNetlistPort(*rfPort, *newInputPort);
1516  if (newOutputPort)
1517  mapNetlistPort(*rfPort, *newOutputPort);
1518  }
1519  if (newInputPort)
1520  mapLoadPort(*newInputPort, *loadPort);
1521  if (newOutputPort)
1522  mapLoadPort(*newOutputPort, *loadPort);
1523 
1524  // add opcode port
1525  NetlistPort* opcodePort = NULL;
1526  if (!port.opcodePort().empty()) {
1527  opcodePort = new NetlistPort(port.opcodePort(),
1528  port.opcodePortWidthFormula(),
1529  MathTools::requiredBits(regFile.numberOfRegisters() - 1),
1530  BIT_VECTOR, IN, *block);
1531  if (newInputPort)
1532  mapRFOpcodePort(*newInputPort, *opcodePort);
1533  if (newOutputPort)
1534  mapRFOpcodePort(*newOutputPort, *opcodePort);
1535  } else if (regFile.numberOfRegisters() == 1) {
1536  // Special case for single register RFs which do not need
1537  // opcode
1538  // port. For legacy support the opcode port is left out if
1539  // opcode
1540  // port field is empty in HDB.
1541  // Do nothing.
1542  } else {
1543  format text("RF entry '%1%' in HDB '%2%' does not have "
1544  "opcode port required for RFs of size > 1.");
1545  text % location.id() % location.hdbFile();
1546  throw InvalidData(__FILE__, __LINE__, __func__, text.str());
1547  }
1548  }
1549 
1550  // add guard port
1551  if (architecture.hasGuardSupport()) {
1552  string guardPortName = implementation.guardPort();
1553  string size;
1554  if (!implementation.sizeParameter().empty()) {
1555  size = implementation.sizeParameter();
1556  } else {
1557  size = Conversion::toString(architecture.size());
1558  }
1559  NetlistPort* guardPort = new NetlistPort(guardPortName, size,
1560  regFile.numberOfRegisters(), BIT_VECTOR, OUT, *block);
1561  mapRFGuardPort(*block, *guardPort);
1562  }
1563 
1564  // Add external ports
1565  string component_type("");
1566  if (dynamic_cast<const ImmediateUnit*>(&regFile) != NULL) {
1567  component_type = IU_NAME_PREFIX;
1568  } else {
1569  component_type = RF_NAME_PREFIX;
1570  }
1571  for (int i = 0; i < implementation.externalPortCount(); i++) {
1572  RFExternalPort& externalPort = implementation.externalPort(i);
1573  // if external port uses parameter, it must be added as netlist
1574  // parameter too and create new width formula for the top-level
1575  // port
1576  // by replacing parameter names with the corresponding names in
1577  // netlist.
1578  string tlPortWidth = externalPort.widthFormula();
1579  for (int i = 0; i < externalPort.parameterDependencyCount(); i++) {
1580  string hdbParamName = externalPort.parameterDependency(i);
1581  Parameter param = block->parameter(hdbParamName);
1582  string nlParamName =
1583  component_type + location.unitName() + "_" + hdbParamName;
1584  if (!targetBlock.netlist().hasParameter(nlParamName)) {
1585  targetBlock.netlist().setParameter(
1586  nlParamName, param.type(), param.value());
1587  }
1588  block->setParameter(param.name(), param.type(), nlParamName);
1589  size_t replaceStart = tlPortWidth.find(param.name(), 0);
1590  if (replaceStart == std::string::npos) {
1591  throw InvalidData(__FILE__, __LINE__, __func__,
1592  (boost::format("RF external port parameter "
1593  "dependencies do not "
1594  "seem "
1595  "to be right: Tried to find "
1596  "parameter named '%s'"
1597  " from external port width formula "
1598  "'%s' in unit "
1599  "'%s'") %
1600  param.name() % tlPortWidth % nlParamName)
1601  .str());
1602  }
1603  size_t replaceLength = param.name().length();
1604  tlPortWidth = tlPortWidth.replace(
1605  replaceStart, replaceLength, nlParamName);
1606  }
1607 
1608  NetlistPort* extPort = new NetlistPort(externalPort.name(),
1609  externalPort.widthFormula(), BIT_VECTOR,
1610  translateDirection(externalPort.direction()), *block);
1611  // connect the external port to top level
1612  string tlPortName = component_type + location.unitName() + "_" +
1613  externalPort.name();
1614  NetlistPort* tlPort =
1615  new NetlistPort(tlPortName, tlPortWidth, BIT_VECTOR,
1616  translateDirection(externalPort.direction()), targetBlock);
1617  targetBlock.netlist().connect(*tlPort, *extPort);
1618  }
1619 
1620  // add clock port
1621  NetlistPort* clockPort =
1622  new NetlistPort(implementation.clkPort(), "1", BIT, IN, *block);
1623  mapClockPort(*block, *clockPort);
1624  // connect clock port
1625  NetlistPort& tlClockPort = clkPort(targetBlock);
1626  targetBlock.netlist().connect(tlClockPort, *clockPort);
1627 
1628  // add reset port
1629  NetlistPort* resetPort =
1630  new NetlistPort(implementation.rstPort(), "1", BIT, IN, *block);
1631  mapResetPort(*block, *resetPort);
1632  // connect reset port
1633  NetlistPort& tlResetPort = rstPort(targetBlock);
1634  targetBlock.netlist().connect(tlResetPort, *resetPort);
1635 
1636  // add glock port
1637  if (implementation.glockPort() != "") {
1638  NetlistPort* glockPort = new NetlistPort(
1639  implementation.glockPort(), "1", BIT, IN, *block);
1640  mapGlobalLockPort(*block, *glockPort);
1641  }
1642  }

References __func__, ProGe::NetlistBlock::addSubBlock(), HDB::RFEntry::architecture(), assert, HDB::BIDIR, ProGe::BIT, ProGe::BIT_VECTOR, checkInstanceName(), clkPort(), ProGe::Netlist::connect(), HDB::RFPortImplementation::direction(), HDB::ExternalPort::direction(), Exception::errorMessage(), glockPort(), HDB::RFEntry::hasArchitecture(), HDB::RFArchitecture::hasGuardSupport(), HDB::RFEntry::hasImplementation(), ProGe::Netlist::hasParameter(), IDF::UnitImplementationLocation::hdbFile(), IDF::UnitImplementationLocation::id(), HDB::RFEntry::implementation(), implementation, HDB::IN, ProGe::IN, TTAMachine::Port::inputSocket(), IU_NAME_PREFIX, HDB::PortImplementation::loadPort(), loadPort(), mapClockPort(), mapGlobalLockPort(), mapImmediateUnitWritePort(), mapLoadPort(), mapNetlistBlock(), mapNetlistPort(), mapResetPort(), mapRFGuardPort(), mapRFOpcodePort(), HDB::Parameter::name, HDB::PortImplementation::name(), HDB::ExternalPort::name(), TTAMachine::Component::name(), ProGe::Parameter::name(), ProGe::NetlistBlock::netlist(), TTAMachine::BaseRegisterFile::numberOfRegisters(), HDB::RFPortImplementation::opcodePort(), HDB::RFPortImplementation::opcodePortWidthFormula(), HDB::OUT, ProGe::OUT, TTAMachine::Port::outputSocket(), ProGe::NetlistBlock::parameter(), HDB::ExternalPort::parameterDependency(), HDB::ExternalPort::parameterDependencyCount(), TTAMachine::BaseRegisterFile::port(), portCorrespondenceMap_, TTAMachine::Unit::portCount(), TCEString::replace(), MathTools::requiredBits(), RF_NAME_PREFIX, HDB::HDBManager::rfByEntryID(), rfEntryMap_, rstPort(), ProGe::NetlistBlock::setParameter(), ProGe::Netlist::setParameter(), HDB::RFArchitecture::size(), Conversion::toString(), translateDirection(), HDB::Parameter::type, ProGe::Parameter::type(), IDF::UnitImplementationLocation::unitName(), HDB::Parameter::value, ProGe::Parameter::value(), TTAMachine::BaseRegisterFile::width(), HDB::RFArchitecture::width(), and HDB::ExternalPort::widthFormula().

Referenced by addIUToNetlist(), and addRFToNetlist().

◆ addFUExternalPortsToNetlist()

void ProGe::NetlistGenerator::addFUExternalPortsToNetlist ( const HDB::FUImplementation &  fuImplementation,
NetlistBlock &  coreBlock,
NetlistBlock &  fuBlock,
const TTAMachine::FunctionUnit &  adfFU 
)
private

Adds external ports defined in HDB into netlist.

Also attempts to recognize LSU memory bus ports and assign them into corresponding NetlistGroup. Recognition is now done by seeking external ports having specific patterns (see inferLSUSignal()).

Definition at line 1189 of file NetlistGenerator.cc.

1191  {
1192 
1193  // external ports recognized as LSU' data memory ports.
1194  set<std::pair<NetlistPort*, NetlistPort*>> lsuPorts;
1195  // Other unrecognized ports.
1196  set<std::pair<NetlistPort*, NetlistPort*>> otherPorts;
1197 
1198  // for each external port, a port is added to top-level block too
1199  for (int i = 0; i < fuImplementation.externalPortCount(); i++) {
1200  FUExternalPort& externalPort = fuImplementation.externalPort(i);
1201  // if external port uses parameter, it must be added as netlist
1202  // parameter too and create new width formula for the top-level
1203  // port
1204  // by replacing parameter names with the corresponding names in
1205  // netlist.
1206  string tlPortWidth = externalPort.widthFormula();
1207  for (int i = 0; i < externalPort.parameterDependencyCount(); i++) {
1208  string paramName = externalPort.parameterDependency(i);
1209  Parameter param = fuBlock.parameter(paramName);
1210  string nlParamName = fuBlock.instanceName() + "_" + paramName;
1211  if (!coreBlock.netlist().hasParameter(nlParamName)) {
1212  coreBlock.netlist().setParameter(
1213  nlParamName, param.type(), param.value());
1214  }
1215  fuBlock.setParameter(param.name(), param.type(), nlParamName);
1216  size_t replaceStart = tlPortWidth.find(param.name(), 0);
1217  if (replaceStart == std::string::npos) {
1218  throw InvalidData(__FILE__, __LINE__, __func__,
1219  (boost::format("FU external port parameter "
1220  "dependencies do not "
1221  "seem "
1222  "to be right: Tried to find "
1223  "parameter named '%s'"
1224  " from external port width formula "
1225  "'%s' in unit "
1226  "'%s'") %
1227  param.name() % tlPortWidth % nlParamName)
1228  .str());
1229  }
1230  size_t replaceLength = param.name().length();
1231  tlPortWidth = tlPortWidth.replace(
1232  replaceStart, replaceLength, nlParamName);
1233  }
1234 
1235  NetlistPort* extPort = new NetlistPort(externalPort.name(),
1236  externalPort.widthFormula(), BIT_VECTOR,
1237  translateDirection(externalPort.direction()), fuBlock);
1238  string tlPortName =
1239  fuBlock.instanceName() + "_" + externalPort.name();
1240  if (isLSUDataPort(adfFU, externalPort.name())) {
1241  NetlistPort* tlPort = new NetlistPort(tlPortName, tlPortWidth,
1242  BIT_VECTOR, translateDirection(externalPort.direction()),
1243  coreBlock, inferLSUSignal(externalPort.name()));
1244  lsuPorts.insert(std::make_pair(extPort, tlPort));
1245  } else {
1246  NetlistPort* tlPort = new NetlistPort(tlPortName, tlPortWidth,
1247  BIT_VECTOR, translateDirection(externalPort.direction()),
1248  coreBlock);
1249  coreBlock.netlist().connect(*extPort, *tlPort);
1250  }
1251  }
1252 
1253  // Handle LSU data ports.
1254  TCEString asName("");
1255  if (adfFU.hasAddressSpace()) {
1256  asName = adfFU.addressSpace()->name();
1257  }
1258 
1259  NetlistPortGroup* dmemPortGroup = nullptr;
1260  for (auto portPair : lsuPorts) {
1261  dmemPortGroup =
1262  dmemPortGroup
1263  ? dmemPortGroup
1264  : (new MemoryBusInterface(
1265  SignalGroupType::BITMASKED_SRAM_PORT, asName));
1266  dmemPortGroup->addPort(*portPair.second);
1267  coreBlock.netlist().connect(*portPair.first, *portPair.second);
1268  }
1269  if (dmemPortGroup != nullptr) {
1270  coreBlock.addPortGroup(dmemPortGroup);
1271  dmemPortGroup = nullptr;
1272  }
1273  }

References __func__, ProGe::NetlistPortGroup::addPort(), ProGe::NetlistBlock::addPortGroup(), TTAMachine::FunctionUnit::addressSpace(), ProGe::BIT_VECTOR, ProGe::BITMASKED_SRAM_PORT, ProGe::Netlist::connect(), HDB::ExternalPort::direction(), HDB::FUImplementation::externalPort(), HDB::FUImplementation::externalPortCount(), TTAMachine::FunctionUnit::hasAddressSpace(), ProGe::Netlist::hasParameter(), inferLSUSignal(), ProGe::BaseNetlistBlock::instanceName(), isLSUDataPort(), HDB::ExternalPort::name(), TTAMachine::Component::name(), ProGe::Parameter::name(), ProGe::NetlistBlock::netlist(), ProGe::NetlistBlock::parameter(), HDB::ExternalPort::parameterDependency(), HDB::ExternalPort::parameterDependencyCount(), TCEString::replace(), ProGe::NetlistBlock::setParameter(), ProGe::Netlist::setParameter(), translateDirection(), ProGe::Parameter::type(), ProGe::Parameter::value(), and HDB::ExternalPort::widthFormula().

Referenced by addFUToNetlist().

Here is the call graph for this function:

◆ addFUToNetlist()

void ProGe::NetlistGenerator::addFUToNetlist ( const IDF::FUImplementationLocation &  location,
NetlistBlock &  coreBlock,
std::ostream &  warningStream 
)
private

Adds the FU identified by the given FUImplementationLocation instance to the netlist.

Parameters
locationThe FUImplementationLocation instance.
netlistThe netlist block under where FU is added.
Exceptions
IOExceptionIf the HDB that contains the implementation cannot be accessed.
InvalidDataIf the MachineImplementation instance is erroneous or if HDB erroneous.

Definition at line 974 of file NetlistGenerator.cc.

976  {
977  string hdbFile = location.hdbFile();
978  int id = location.id();
979  FUEntry* entry = NULL;
980 
981  try {
982  HDBManager& manager = HDBRegistry::instance().hdb(hdbFile);
983  entry = manager.fuByEntryID(id);
984  } catch (const KeyNotFound& e) {
985  throw InvalidData(__FILE__, __LINE__, __func__, e.errorMessage());
986  }
987 
988  if (!entry->hasImplementation() || !entry->hasArchitecture()) {
989  string errorMsg;
990  if (!entry->hasImplementation()) {
991  errorMsg = "FU entry " + Conversion::toString(id) +
992  " does not "
993  "have an implementation in HDB " +
994  hdbFile + ".";
995  } else {
996  errorMsg = "FU entry " + Conversion::toString(id) +
997  " does not "
998  "have architecture definition in HDB " +
999  hdbFile + ".";
1000  }
1001  throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
1002  }
1003 
1004  if (!context_.adf().functionUnitNavigator().hasItem(
1005  location.unitName())) {
1006  string errorMsg = "ADF does not have FU '" + location.unitName() +
1007  "' which is referred to in the IDF.";
1008  throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
1009  }
1010 
1011  fuEntryMap_.insert(std::make_pair(location.unitName(), entry));
1012  FUImplementation& fuImplementation = entry->implementation();
1013  FUArchitecture& architecture = entry->architecture();
1014  const FunctionUnit* adfFU =
1015  context_.adf().functionUnitNavigator().item(location.unitName());
1016  TCEString instanceName = FU_NAME_PREFIX + location.unitName();
1017  TCEString moduleName = fuImplementation.moduleName();
1018  instanceName = checkInstanceName(instanceName, moduleName);
1019  NetlistBlock* block = new NetlistBlock(moduleName, instanceName);
1020  coreBlock.addSubBlock(block);
1021  mapNetlistBlock(*adfFU, *block);
1022 
1023  format architecturesDontMatch("Architectures of FU entry %1% in "
1024  "%2% and FU '%3%' don't match.");
1025 
1026  // add parameters
1027  for (int i = 0; i < fuImplementation.parameterCount(); i++) {
1028  FUImplementation::Parameter parameter =
1029  fuImplementation.parameter(i);
1030  string paramName = parameter.name;
1031  string paramType = parameter.type;
1032  string paramValue = parameter.value;
1033  if (paramValue == "" || isParameterizable(paramName, entry)) {
1034  bool parameterResolved = false;
1035  // find the port which uses this parameter
1036  for (int j = 0; j < fuImplementation.architecturePortCount();
1037  j++) {
1038  FUPortImplementation& port =
1039  fuImplementation.architecturePort(j);
1040 
1041  // Special case if the FU is an LSU and it has
1042  // parametrizable
1043  // address width. This sets the ADF port width according
1044  // to
1045  // address space width in ADF
1046  if (adfFU->hasAddressSpace() && isLSU(*adfFU)) {
1047  FUPort& adfPort = findCorrespondingPort(*adfFU,
1048  architecture.architecture(),
1049  port.architecturePort());
1050  // Assume address port is the triggering port
1051  if (adfPort.isTriggering() &&
1052  port.widthFormula() == paramName) {
1053  int ASWidth = calculateAddressWidth(adfFU);
1054  block->setParameter(paramName, paramType,
1055  Conversion::toString(ASWidth));
1056  // Fix the FU port width
1057  adfPort.setWidth(ASWidth);
1058  parameterResolved = true;
1059  break;
1060  }
1061  }
1062  if (port.widthFormula() == paramName) {
1063  try {
1064  FUPort& adfPort = findCorrespondingPort(*adfFU,
1065  architecture.architecture(),
1066  port.architecturePort());
1067  block->setParameter(paramName, paramType,
1068  Conversion::toString(adfPort.width()));
1069  parameterResolved = true;
1070  break;
1071  } catch (const InstanceNotFound&) {
1072  architecturesDontMatch % id % hdbFile %
1073  adfFU->name();
1074  throw InvalidData(__FILE__, __LINE__, __func__,
1075  architecturesDontMatch.str());
1076  }
1077  }
1078  }
1079 
1080  if (!parameterResolved) {
1081  format errorMsg("Unable to resolve the value of "
1082  "parameter %1% of FU "
1083  "entry %2%.");
1084  errorMsg % paramName % id;
1085  throw InvalidData(
1086  __FILE__, __LINE__, __func__, errorMsg.str());
1087  }
1088 
1089  } else {
1090  block->setParameter(paramName, paramType, paramValue);
1091  }
1092  }
1093 
1094  // add ports to the netlist block
1095  for (int i = 0; i < fuImplementation.architecturePortCount(); i++) {
1096 
1097  FUPortImplementation& port = fuImplementation.architecturePort(i);
1098 
1099  // add architectural port
1100  string architecturePort = port.architecturePort();
1101 
1102  FUPort* adfPort;
1103  try {
1104  adfPort = &findCorrespondingPort(
1105  *adfFU, architecture.architecture(), architecturePort);
1106  } catch (const InstanceNotFound&) {
1107  architecturesDontMatch % id % hdbFile % adfFU->name();
1108  throw InvalidData(
1109  __FILE__, __LINE__, __func__, architecturesDontMatch.str());
1110  }
1111  NetlistPort* newPort = new NetlistPort(port.name(),
1112  port.widthFormula(), adfPort->width(), BIT_VECTOR,
1113  translateDirection(
1114  architecture.portDirection(architecturePort)),
1115  *block);
1116  mapNetlistPort(*adfPort, *newPort);
1117 
1118  // add load port
1119  if (port.loadPort() != "") {
1120  NetlistPort* loadPort =
1121  new NetlistPort(port.loadPort(), "1", 1, BIT, IN, *block);
1122  mapLoadPort(*newPort, *loadPort);
1123  }
1124 
1125  // add guard port
1126  if (port.guardPort() != "") {
1127  NetlistPort* guardPort =
1128  new NetlistPort(port.guardPort(), "1", 1, BIT, OUT, *block);
1129  mapFUGuardPort(*newPort, *guardPort);
1130  }
1131  }
1132 
1133  // add opcode port
1134  if (fuImplementation.opcodePort() != "") {
1135  NetlistPort* opcodePort = new NetlistPort(
1136  fuImplementation.opcodePort(),
1137  Conversion::toString(opcodePortWidth(*entry, warningStream)),
1138  opcodePortWidth(*entry, warningStream), BIT_VECTOR, IN, *block);
1139  mapFUOpcodePort(*block, *opcodePort);
1140  }
1141 
1142  // add external ports
1143  addFUExternalPortsToNetlist(
1144  fuImplementation, coreBlock, *block, *adfFU);
1145 
1146  // add clock port
1147  if (fuImplementation.clkPort() != "") {
1148  NetlistPort* clkPort = new NetlistPort(
1149  fuImplementation.clkPort(), "1", 1, BIT, IN, *block);
1150  mapClockPort(*block, *clkPort);
1151  // connect clock port
1152  NetlistPort& tlClkPort = this->clkPort(coreBlock);
1153  coreBlock.netlist().connect(*clkPort, tlClkPort);
1154  }
1155 
1156  // add reset port
1157  if (fuImplementation.rstPort() != "") {
1158  NetlistPort* rstPort = new NetlistPort(
1159  fuImplementation.rstPort(), "1", 1, BIT, IN, *block);
1160  mapResetPort(*block, *rstPort);
1161  // connect reset port
1162  NetlistPort& tlRstPort = this->rstPort(coreBlock);
1163  coreBlock.netlist().connect(*rstPort, tlRstPort);
1164  }
1165 
1166  // add global lock port
1167  if (fuImplementation.glockPort() != "") {
1168  NetlistPort* glockPort = new NetlistPort(
1169  fuImplementation.glockPort(), "1", 1, BIT, IN, *block);
1170  mapGlobalLockPort(*block, *glockPort);
1171  }
1172 
1173  // add global lock request port
1174  if (fuImplementation.glockReqPort() != "") {
1175  NetlistPort* glockReqPort = new NetlistPort(
1176  fuImplementation.glockReqPort(), "1", 1, BIT, OUT, *block);
1177  mapGlobalLockRequestPort(*block, *glockReqPort);
1178  }
1179  }

References __func__, addFUExternalPortsToNetlist(), ProGe::NetlistBlock::addSubBlock(), ProGe::ProGeContext::adf(), HDB::FUEntry::architecture(), HDB::FUArchitecture::architecture(), HDB::FUPortImplementation::architecturePort(), HDB::FUImplementation::architecturePort(), HDB::FUImplementation::architecturePortCount(), ProGe::BIT, ProGe::BIT_VECTOR, calculateAddressWidth(), checkInstanceName(), HDB::HWBlockImplementation::clkPort(), clkPort(), ProGe::Netlist::connect(), context_, Exception::errorMessage(), findCorrespondingPort(), FU_NAME_PREFIX, HDB::HDBManager::fuByEntryID(), fuEntryMap_, TTAMachine::Machine::functionUnitNavigator(), HDB::HWBlockImplementation::glockPort(), glockPort(), HDB::FUImplementation::glockReqPort(), glockReqPort(), HDB::FUPortImplementation::guardPort(), TTAMachine::FunctionUnit::hasAddressSpace(), HDB::FUEntry::hasArchitecture(), HDB::FUEntry::hasImplementation(), TTAMachine::Machine::Navigator< ComponentType >::hasItem(), IDF::UnitImplementationLocation::hdbFile(), IDF::UnitImplementationLocation::id(), HDB::FUEntry::implementation(), ProGe::IN, isLSU(), isParameterizable(), TTAMachine::FUPort::isTriggering(), TTAMachine::Machine::Navigator< ComponentType >::item(), HDB::PortImplementation::loadPort(), loadPort(), mapClockPort(), mapFUGuardPort(), mapFUOpcodePort(), mapGlobalLockPort(), mapGlobalLockRequestPort(), mapLoadPort(), mapNetlistBlock(), mapNetlistPort(), mapResetPort(), HDB::HWBlockImplementation::moduleName(), HDB::Parameter::name, HDB::PortImplementation::name(), TTAMachine::Component::name(), ProGe::NetlistBlock::netlist(), HDB::FUImplementation::opcodePort(), opcodePortWidth(), ProGe::OUT, HDB::FUImplementation::parameter(), HDB::FUImplementation::parameterCount(), HDB::FUArchitecture::portDirection(), HDB::HWBlockImplementation::rstPort(), rstPort(), ProGe::NetlistBlock::setParameter(), TTAMachine::BaseFUPort::setWidth(), Conversion::toString(), translateDirection(), HDB::Parameter::type, IDF::UnitImplementationLocation::unitName(), HDB::Parameter::value, TTAMachine::BaseFUPort::width(), and HDB::FUPortImplementation::widthFormula().

Referenced by generate().

◆ addGCUToNetlist()

void ProGe::NetlistGenerator::addGCUToNetlist ( NetlistBlock &  toplevelBlock,
int  imemWidthInMAUs 
)
private

Adds the global control unit to the netlist as sub-block of the given top-level block.

Parameters
toplevelBlockThe top-level block of the netlist.
imemWidthInMAUsWidth of the instruction memory in MAUs.

Definition at line 692 of file NetlistGenerator.cc.

693  {
694  if (imemWidthInMAUs != 4 && context_.adf().isRISCVMachine()) {
695  throw InvalidData(__FILE__, __LINE__, __func__,
696  "Imem width fixed to 4 MAUs for RISC-V machines");
697  } else if (imemWidthInMAUs != 1 && !context_.adf().isRISCVMachine()) {
698  throw InvalidData(__FILE__, __LINE__, __func__,
699  "Imem width is currently fixed to 1 MAU");
700  }
701  Netlist& netlist = toplevelBlock.netlist();
702 
703  Parameter coreIdParam("core_id", "integer", "0", "0");
704  toplevelBlock.addParameter(coreIdParam);
705 
706  NetlistPort* tlClkPort =
707  new InBitPort(CLOCK_PORT_NAME, toplevelBlock, SignalType::CLOCK);
708  NetlistPort* tlRstPort = new InBitPort(RESET_PORT_NAME, toplevelBlock,
709  Signal(SignalType::RESET, ActiveState::LOW));
710 
711  // Instruction fetch bus //
712  NetlistPort* tlBusyPort = new InBitPort(BUSY_PORT_NAME,
713  Signal(SignalType::READ_REQUEST_READY, ActiveState::LOW));
714  NetlistPort* tlReadEnablePort = new OutBitPort(READ_ENABLE_PORT_NAME,
715  Signal(SignalType::READ_REQUEST, ActiveState::LOW));
716  NetlistPort* tlAddressPort = new OutPort(ADDRESS_PORT_NAME,
717  IMEMADDRWIDTH, BIT_VECTOR, Signal(SignalType::ADDRESS));
718  NetlistPort* tlDataPort = new InPort(DATA_PORT_NAME, IMEMWIDTHFORMULA,
719  BIT_VECTOR, Signal(SignalType::FETCHBLOCK));
720  NetlistPortGroup* toplevelInstructionLine =
721  new NetlistPortGroup(SignalGroupType::INSTRUCTION_LINE, tlBusyPort,
722  tlReadEnablePort, tlAddressPort, tlDataPort);
723  toplevelBlock.addPortGroup(toplevelInstructionLine);
724 
725  NetlistPort* tlLockStatusPort = new NetlistPort(LOCK_STATUS_PORT_NAME,
726  "1", BIT, OUT, toplevelBlock, SignalType::CORE_HALT_STATUS);
727 
728  mapClockPort(toplevelBlock, *tlClkPort);
729  mapResetPort(toplevelBlock, *tlRstPort);
730 
731  // add ifetch block
732  ControlUnit* gcu = context_.adf().controlUnit();
733  instructionFetch_ = new NetlistBlock(
734  context_.coreEntityName() + "_" + IFETCH_BLOCK_NAME, "inst_fetch");
735  toplevelBlock.addSubBlock(instructionFetch_);
736  NetlistPort* ifetchClkPort =
737  new NetlistPort(CLOCK_PORT_NAME, "1", BIT, IN, *instructionFetch_);
738  NetlistPort* ifetchRstPort =
739  new NetlistPort(RESET_PORT_NAME, "1", BIT, IN, *instructionFetch_);
740  NetlistPort* ifetchRAOutPort = new NetlistPort(RA_OUT_PORT_NAME,
741  IMEMADDRWIDTH, BIT_VECTOR, OUT, *instructionFetch_);
742  raOutPort_ = ifetchRAOutPort;
743  NetlistPort* ifetchRAInPort = new NetlistPort(
744  RA_IN_PORT_NAME, IMEMADDRWIDTH, BIT_VECTOR, IN, *instructionFetch_);
745  raInPort_ = ifetchRAInPort;
746 
747  NetlistPort* ifetchBusyPort = new InBitPort(BUSY_PORT_NAME,
748  Signal(SignalType::READ_REQUEST_READY, ActiveState::LOW));
749  NetlistPort* ifetchReadEnablePort =
750  new OutBitPort(READ_ENABLE_PORT_NAME,
751  Signal(SignalType::READ_REQUEST, ActiveState::LOW));
752  NetlistPort* ifetchAddressPort = new OutPort(ADDRESS_PORT_NAME,
753  IMEMADDRWIDTH, BIT_VECTOR, Signal(SignalType::ADDRESS));
754  NetlistPort* ifetchDataPort = new InPort(DATA_PORT_NAME,
755  IMEMWIDTHFORMULA, BIT_VECTOR, Signal(SignalType::FETCHBLOCK));
756  NetlistPortGroup* ifetchInstructionLine = new NetlistPortGroup(
757  SignalGroupType::INSTRUCTION_LINE, ifetchBusyPort,
758  ifetchReadEnablePort, ifetchAddressPort, ifetchDataPort);
759  instructionFetch_->addPortGroup(ifetchInstructionLine);
760 
761  NetlistPort* ifetchPCInPort = new NetlistPort(
762  PC_IN_PORT_NAME, IMEMADDRWIDTH, BIT_VECTOR, IN, *instructionFetch_);
763  NetlistPort* ifetchPCLoadPort = new NetlistPort(
764  PC_LOAD_PORT_NAME, "1", BIT, IN, *instructionFetch_);
765  NetlistPort* ifetchRALoadPort = new NetlistPort(
766  RA_LOAD_PORT_NAME, "1", BIT, IN, *instructionFetch_);
767  NetlistPort* ifetchPCOpcodePort = new NetlistPort(PC_OPCODE_PORT_NAME,
768  Conversion::toString(opcodePortWidth(*gcu)), opcodePortWidth(*gcu),
769  BIT_VECTOR, IN, *instructionFetch_);
770  NetlistPort* ifetchFetchPort =
771  new NetlistPort(FETCH_PORT_NAME, "1", BIT, IN, *instructionFetch_);
772  NetlistPort* ifetchGlockPort = new NetlistPort(
773  GLOBAL_LOCK_PORT_NAME, "1", BIT, OUT, *instructionFetch_);
774  NetlistPort* ifetchFetchBlockPort =
775  new NetlistPort(FETCHBLOCK_PORT_NAME, IMEMWIDTHFORMULA, BIT_VECTOR,
776  OUT, *instructionFetch_);
777 
778  // connect ifetch to toplevel
779  netlist.connect(*tlClkPort, *ifetchClkPort);
780  netlist.connect(*tlRstPort, *ifetchRstPort);
781 
782  netlist.connect(*toplevelInstructionLine, *ifetchInstructionLine);
783 
784  if (gcu->operationPortCount() > 0) {
785  mapNetlistPort(*gcu->triggerPort(), *ifetchPCInPort);
786  }
787 
788  // Add non-standard GCU ports to the block.
789  for (int i = 0; i < gcu->portCount(); i++) {
790  Port* port = gcu->port(i);
791  if (gcu->returnAddressPort()->name() == port->name()) {
792  continue;
793  }
794  if (!netlistPortIsMapped(*port)) {
795  Direction dir;
796  if (port->isInput()) {
797  dir = IN;
798  } else if (port->isOutput()) {
799  dir = OUT;
800  } else {
801  assert(false && "Unconneced ADF port.");
802  }
803  // Data port
804  NetlistPort* dataPort = new NetlistPort(port->name() + "_data",
805  Conversion::toString(port->width()), BIT_VECTOR, dir,
806  *instructionFetch_);
807  mapNetlistPort(*port, *dataPort);
808 
809  // Load port if port is input
810  if (port->isInput()) {
811  NetlistPort* loadPort =
812  new NetlistPort(port->name() + "_load", "1", BIT, dir,
813  *instructionFetch_);
814  mapLoadPort(*dataPort, *loadPort);
815  }
816  }
817  }
818 
819  // add decompressor block
820  NetlistBlock* decompressorBlock = new NetlistBlock(
821  context_.coreEntityName() + "_" + DECOMPRESSOR_BLOCK_NAME,
822  "decomp");
823  instructionDecompressor_ = decompressorBlock;
824  toplevelBlock.addSubBlock(decompressorBlock);
825  NetlistPort* decFetchPort =
826  new NetlistPort(FETCH_PORT_NAME, "1", BIT, OUT, *decompressorBlock);
827  NetlistPort* decLockPort =
828  new NetlistPort(LOCK_PORT_NAME, "1", BIT, IN, *decompressorBlock);
829  NetlistPort* decFetchBlockPort = new NetlistPort(FETCHBLOCK_PORT_NAME,
830  IMEMWIDTHFORMULA, BIT_VECTOR, IN, *decompressorBlock);
831  NetlistPort* decClkPort =
832  new NetlistPort(CLOCK_PORT_NAME, "1", BIT, IN, *decompressorBlock);
833  NetlistPort* decRstPort =
834  new NetlistPort(RESET_PORT_NAME, "1", BIT, IN, *decompressorBlock);
835  NetlistPort* decIWordPort = new NetlistPort(INSTRUCTIONWORD_PORT_NAME,
836  INSTRUCTIONWIDTH, BIT_VECTOR, OUT, *decompressorBlock);
837  NetlistPort* decGlockPort = new NetlistPort(
838  GLOBAL_LOCK_PORT_NAME, "1", BIT, OUT, *decompressorBlock);
839  NetlistPort* decLockReqPort = new NetlistPort(
840  LOCK_REQUEST_PORT_NAME, "1", BIT, IN, *decompressorBlock);
841 
842  // connect ifetch to decompressor
843  netlist.connect(*ifetchFetchPort, *decFetchPort);
844  netlist.connect(*ifetchGlockPort, *decLockPort);
845  netlist.connect(*ifetchFetchBlockPort, *decFetchBlockPort);
846 
847  // connect toplevel to decompressor
848  netlist.connect(*tlClkPort, *decClkPort);
849  netlist.connect(*tlRstPort, *decRstPort);
850 
851  // add decoder block
852  NetlistBlock* decoderBlock = new NetlistBlock(
853  context_.coreEntityName() + "_" + DECODER_BLOCK_NAME,
854  "inst_decoder");
855  toplevelBlock.addSubBlock(decoderBlock);
856  instructionDecoder_ = decoderBlock;
857  NetlistPort* decodIWordPort = new NetlistPort(DECODER_INSTR_WORD_PORT,
858  INSTRUCTIONWIDTH, BIT_VECTOR, IN, *decoderBlock);
859  NetlistPort* decodPCLoadPort =
860  new NetlistPort(DECODER_PC_LOAD_PORT, "1", BIT, OUT, *decoderBlock);
861  NetlistPort* decodRALoadPort =
862  new NetlistPort(DECODER_RA_LOAD_PORT, "1", BIT, OUT, *decoderBlock);
863  NetlistPort* decodPCOpcodePort = new NetlistPort(DECODER_PC_OPCODE_PORT,
864  Conversion::toString(opcodePortWidth(*gcu)), opcodePortWidth(*gcu),
865  BIT_VECTOR, OUT, *decoderBlock);
866  NetlistPort* decodLockPort = new NetlistPort(
867  DECODER_LOCK_REQ_IN_PORT, "1", BIT, IN, *decoderBlock);
868  NetlistPort* decodLockReqPort = new NetlistPort(
869  DECODER_LOCK_REQ_OUT_PORT, "1", BIT, OUT, *decoderBlock);
870  NetlistPort* decodClkPort =
871  new NetlistPort(DECODER_CLOCK_PORT, "1", BIT, IN, *decoderBlock);
872  NetlistPort* decodRstPort =
873  new NetlistPort(DECODER_RESET_PORT, "1", BIT, IN, *decoderBlock);
874  NetlistPort* decodLockedPort = new NetlistPort(
875  DECODER_LOCK_STATUS_PORT, "1", BIT, OUT, *decoderBlock);
876 
877  // connect decoder to decompressor
878  netlist.connect(*decIWordPort, *decodIWordPort);
879  netlist.connect(*decGlockPort, *decodLockPort);
880  netlist.connect(*decLockReqPort, *decodLockReqPort);
881 
882  // connect decoder to top-level
883  netlist.connect(*decodClkPort, *tlClkPort);
884  netlist.connect(*decodRstPort, *tlRstPort);
885 
886  // connect decoder to ifetch
887  netlist.connect(*decodPCLoadPort, *ifetchPCLoadPort);
888  netlist.connect(*decodRALoadPort, *ifetchRALoadPort);
889  netlist.connect(*decodPCOpcodePort, *ifetchPCOpcodePort);
890 
891  // connect lock status signal port
892  netlist.connect(*tlLockStatusPort, *decodLockedPort);
893 
894  Netlist::connectClocks(toplevelBlock);
895  Netlist::connectResets(toplevelBlock);
896  }

References __func__, ProGe::NetlistBlock::addParameter(), ProGe::NetlistBlock::addPortGroup(), ProGe::ADDRESS, ADDRESS_PORT_NAME, ProGe::NetlistBlock::addSubBlock(), ProGe::ProGeContext::adf(), assert, ProGe::BIT, ProGe::BIT_VECTOR, BUSY_PORT_NAME, ProGe::CLOCK, CLOCK_PORT_NAME, ProGe::Netlist::connect(), ProGe::Netlist::connectClocks(), ProGe::Netlist::connectResets(), context_, TTAMachine::Machine::controlUnit(), ProGe::CORE_HALT_STATUS, ProGe::ProGeContext::coreEntityName(), DATA_PORT_NAME, DECODER_BLOCK_NAME, DECODER_CLOCK_PORT, DECODER_INSTR_WORD_PORT, DECODER_LOCK_REQ_IN_PORT, DECODER_LOCK_REQ_OUT_PORT, DECODER_LOCK_STATUS_PORT, DECODER_PC_LOAD_PORT, DECODER_PC_OPCODE_PORT, DECODER_RA_LOAD_PORT, DECODER_RESET_PORT, DECOMPRESSOR_BLOCK_NAME, FETCH_PORT_NAME, ProGe::FETCHBLOCK, FETCHBLOCK_PORT_NAME, GLOBAL_LOCK_PORT_NAME, IFETCH_BLOCK_NAME, IMEMADDRWIDTH, IMEMWIDTHFORMULA, ProGe::IN, ProGe::INSTRUCTION_LINE, instructionDecoder_, instructionDecompressor_, instructionFetch_, INSTRUCTIONWIDTH, INSTRUCTIONWORD_PORT_NAME, TTAMachine::Port::isInput(), TTAMachine::Port::isOutput(), TTAMachine::Machine::isRISCVMachine(), loadPort(), LOCK_PORT_NAME, LOCK_REQUEST_PORT_NAME, LOCK_STATUS_PORT_NAME, ProGe::LOW, mapClockPort(), mapLoadPort(), mapNetlistPort(), mapResetPort(), TTAMachine::Port::name(), ProGe::NetlistBlock::netlist(), netlistPortIsMapped(), opcodePortWidth(), TTAMachine::FunctionUnit::operationPortCount(), ProGe::OUT, PC_IN_PORT_NAME, PC_LOAD_PORT_NAME, PC_OPCODE_PORT_NAME, TTAMachine::FunctionUnit::port(), TTAMachine::Unit::portCount(), RA_IN_PORT_NAME, RA_LOAD_PORT_NAME, RA_OUT_PORT_NAME, raInPort_, raOutPort_, READ_ENABLE_PORT_NAME, ProGe::READ_REQUEST, ProGe::READ_REQUEST_READY, ProGe::RESET, RESET_PORT_NAME, TTAMachine::ControlUnit::returnAddressPort(), Conversion::toString(), TTAMachine::FunctionUnit::triggerPort(), and TTAMachine::Port::width().

Referenced by generate().

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◆ addGeneratableFUsToNetlist()

GeneratableFUNetlistBlock * ProGe::NetlistGenerator::addGeneratableFUsToNetlist ( const IDF::FUGenerated &  fug,
NetlistBlock &  netlistBlock 
)
private

Definition at line 898 of file NetlistGenerator.cc.

899  {
900 
901  std::string fuName = "fu_" + fug.name();
902  std::transform(fuName.begin(), fuName.end(), fuName.begin(), ::tolower);
903 
904  GeneratableFUNetlistBlock* block = new GeneratableFUNetlistBlock(
905  fuName, fuName + "_generated", *this);
906  coreBlock.addSubBlock(block);
907 
908  FunctionUnit* fu =
909  context_.adf().functionUnitNavigator().item(fug.name());
910 
911  mapNetlistBlock(*fu, *block);
912 
913  // add clock port
914  NetlistPort* clkPort = new NetlistPort("clk", "1", 1, BIT, IN, *block);
915  mapClockPort(*block, *clkPort);
916  // connect clock port
917  NetlistPort& tlClkPort = this->clkPort(coreBlock);
918  coreBlock.netlist().connect(*clkPort, tlClkPort);
919 
920  // add reset port
921  NetlistPort* rstPort = new NetlistPort("rstx", "1", 1, BIT, IN, *block);
922  mapResetPort(*block, *rstPort);
923  // connect reset port
924  NetlistPort& tlRstPort = this->rstPort(coreBlock);
925  coreBlock.netlist().connect(*rstPort, tlRstPort);
926 
927  // add global lock port
928  NetlistPort* glockPort =
929  new NetlistPort("glock_in", "1", 1, BIT, IN, *block);
930  mapGlobalLockPort(*block, *glockPort);
931 
932  // opcode port.
933  int opcodeWidth = static_cast<int>(std::ceil(
934  std::log2(fu->operationCount())));
935  if (fu->operationCount() > 1) {
936  NetlistPort* opcodePort = new NetlistPort("operation_in",
937  std::to_string(opcodeWidth), BIT_VECTOR, IN, *block);
938  mapFUOpcodePort(*block, *opcodePort);
939  }
940 
941  // global lock request port
942  NetlistPort* glockReqPort = new NetlistPort(
943  "glockreq_out", "1", 1, BIT, OUT, *block);
944  mapGlobalLockRequestPort(*block, *glockReqPort);
945 
946  // operand ports.
947  for (int i = 0; i < fu->portCount(); ++i) {
948  FUPort* adfPort = dynamic_cast<FUPort*>(fu->port(i));
949 
950  if (adfPort->isInput()) {
951  block->addInOperand(adfPort, i);
952  } else {
953  block->addOutOperand(adfPort);
954  }
955  }
956 
957  return block;
958  }

References ProGe::GeneratableFUNetlistBlock::addInOperand(), ProGe::GeneratableFUNetlistBlock::addOutOperand(), ProGe::NetlistBlock::addSubBlock(), ProGe::ProGeContext::adf(), ProGe::BIT, ProGe::BIT_VECTOR, clkPort(), ProGe::Netlist::connect(), context_, TTAMachine::Machine::functionUnitNavigator(), GeneratableFUNetlistBlock, glockPort(), glockReqPort(), ProGe::IN, TTAMachine::Port::isInput(), TTAMachine::Machine::Navigator< ComponentType >::item(), mapClockPort(), mapFUOpcodePort(), mapGlobalLockPort(), mapGlobalLockRequestPort(), mapNetlistBlock(), mapResetPort(), IDF::FUGenerated::name(), ProGe::NetlistBlock::netlist(), TTAMachine::FunctionUnit::operationCount(), ProGe::OUT, TTAMachine::FunctionUnit::port(), TTAMachine::Unit::portCount(), and rstPort().

Referenced by generate().

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◆ addIUToNetlist()

void ProGe::NetlistGenerator::addIUToNetlist ( const ProGeOptions &  options,
const IDF::RFImplementationLocation &  location,
NetlistBlock &  netlistBlock 
)
private

Adds the IU identified by the given RFImplementationLocation instance to the netlist.

Parameters
locationThe RFImplementationLocation instance.
netlistThe netlist.
Exceptions
IOExceptionIf the HDB that contains the implementation cannot be accessed.
InvalidDataIf the MachineImplementation instance or HDB is erroneous.

Definition at line 1318 of file NetlistGenerator.cc.

1320  {
1321  if (!context_.adf().immediateUnitNavigator().hasItem(
1322  location.unitName())) {
1323  string errorMsg = "ADF does not contain immediate unit '" +
1324  location.unitName() + "' referred to in IDF.";
1325  throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
1326  }
1327  ImmediateUnit* iu =
1328  context_.adf().immediateUnitNavigator().item(location.unitName());
1329  addBaseRFToNetlist(options, *iu, location, netlistBlock,
1330  IU_NAME_PREFIX);
1331  }

References __func__, addBaseRFToNetlist(), ProGe::ProGeContext::adf(), context_, TTAMachine::Machine::Navigator< ComponentType >::hasItem(), TTAMachine::Machine::immediateUnitNavigator(), TTAMachine::Machine::Navigator< ComponentType >::item(), IU_NAME_PREFIX, netlistBlock(), options, and IDF::UnitImplementationLocation::unitName().

Referenced by generate().

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◆ addRFToNetlist()

void ProGe::NetlistGenerator::addRFToNetlist ( const ProGeOptions &  options,
const IDF::RFImplementationLocation &  location,
NetlistBlock &  netlistBlock 
)
private

Adds the RF identified by the given RFImplementationLocation instance to the netlist.

Parameters
locationThe RFImplementationLocation instance.
netlistThe netlist.
Exceptions
IOExceptionIf the HDB that contains the implementation cannot be accessed.
InvalidDataIf the MachineImplementation instance or HDB is erroneous.

Definition at line 1289 of file NetlistGenerator.cc.

1291  {
1292  if (!context_.adf().registerFileNavigator().hasItem(
1293  location.unitName())) {
1294  string errorMsg = "ADF does not contain register file '" +
1295  location.unitName() + "' referred to in IDF.";
1296  throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
1297  }
1298  RegisterFile* rf =
1299  context_.adf().registerFileNavigator().item(location.unitName());
1300  addBaseRFToNetlist(options, *rf, location, netlistBlock,
1301  RF_NAME_PREFIX);
1302  }

References __func__, addBaseRFToNetlist(), ProGe::ProGeContext::adf(), context_, TTAMachine::Machine::Navigator< ComponentType >::hasItem(), TTAMachine::Machine::Navigator< ComponentType >::item(), netlistBlock(), options, TTAMachine::Machine::registerFileNavigator(), RF_NAME_PREFIX, and IDF::UnitImplementationLocation::unitName().

Referenced by generate().

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◆ calculateAddressWidth()

unsigned int ProGe::NetlistGenerator::calculateAddressWidth ( TTAMachine::FunctionUnit const *  fu) const
private

Calculates the address width of an address space in FU

Exceptions
Invaliddata If the FU doesn't have an address space or the address space is invalid

Definition at line 1856 of file NetlistGenerator.cc.

1857  {
1858  if (fu->hasAddressSpace() && fu->addressSpace() != NULL) {
1859  AddressSpace* AS = fu->addressSpace();
1860  unsigned int highestAddr = AS->end();
1861  unsigned int lowestAddr = AS->start();
1862  if (highestAddr == 0 || lowestAddr >= highestAddr) {
1863  string errorMessage = "Invalid address space";
1864  throw InvalidData(
1865  __FILE__, __LINE__, __func__, errorMessage.c_str());
1866  }
1867  return static_cast<unsigned int>(ceil(log(highestAddr) / log(2)));
1868  } else {
1869  string errorMessage = "Tried to resolve address space width "
1870  "from FU '" +
1871  fu->name() +
1872  "' that doesn't have address space";
1873  throw InvalidData(
1874  __FILE__, __LINE__, __func__, errorMessage.c_str());
1875  }
1876  // never reached
1877  return 0;
1878  }

References __func__, TTAMachine::FunctionUnit::addressSpace(), TTAMachine::AddressSpace::end(), TTAMachine::FunctionUnit::hasAddressSpace(), TTAMachine::Component::name(), and TTAMachine::AddressSpace::start().

Referenced by addFUToNetlist().

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◆ checkInstanceName()

TCEString ProGe::NetlistGenerator::checkInstanceName ( const TCEString &  baseInstanceName,
const TCEString &  moduleName 
) const
private

Return fixed instance name if instance name is equal to module name.

Parameters
baseInstanceNameDefault name for a component instance
moduleNameName for the component module defined in HDB
Returns
Instance name differing from the module name.

Definition at line 2080 of file NetlistGenerator.cc.

2081  {
2082 
2083  TCEString newInstanceName;
2084  if (baseInstanceName.lower() == moduleName.lower()) {
2085  newInstanceName = baseInstanceName + INSTANCE_SUFFIX;
2086  } else {
2087  newInstanceName = baseInstanceName;
2088  }
2089  return newInstanceName;
2090  }

References INSTANCE_SUFFIX, and TCEString::lower().

Referenced by addBaseRFToNetlist(), and addFUToNetlist().

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◆ clkPort()

NetlistPort & ProGe::NetlistGenerator::clkPort ( const NetlistBlock &  block) const

Returns the clock port of the given block in the netlist.

Parameters
blockThe block in the netlist.
Returns
The clock port of the given block.
Exceptions
InstanceNotFoundIf the netlist does not contain the port.

Definition at line 425 of file NetlistGenerator.cc.

425  {
426  try {
427  return *MapTools::valueForKey<NetlistPort*>(clkPorts_, &block);
428  } catch (const Exception&) {
429  throw InstanceNotFound(__FILE__, __LINE__, __func__,
430  (boost::format("Cannot find clock port in netlist block "
431  "instance name: "
432  "'%s', module name: '%s'") %
433  block.instanceName() % block.moduleName())
434  .str());
435  }
436  }

References __func__, clkPorts_, ProGe::BaseNetlistBlock::instanceName(), and ProGe::BaseNetlistBlock::moduleName().

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGeneratableFUsToNetlist(), DefaultICDecoderGenerator::addRV32MicroCode(), DefaultICDecoderGenerator::generateDebuggerCode(), and mapClockPort().

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◆ context()

const ProGeContext& ProGe::NetlistGenerator::context ( ) const
inline

Definition at line 125 of file NetlistGenerator.hh.

125 { return context_; }

References context_.

Referenced by DefaultICDecoderGenerator::generate().

◆ findCorrespondingPort()

TTAMachine::FUPort & ProGe::NetlistGenerator::findCorrespondingPort ( const TTAMachine::FunctionUnit &  fuToSearch,
const TTAMachine::FunctionUnit &  origFU,
const std::string &  portName 
)
staticprivate

Finds the corresponding ports from the given function units.

Parameters
fuToSearchThe FU that is searched for the corresponding port.
origFUThe original FU.
portNameName of the port in the original FU.
Returns
The corresponding port in fuToSearch FU.
Exceptions
InstanceNotFoundIf there is no corresponding port.

Definition at line 1963 of file NetlistGenerator.cc.

1965  {
1966  FUPort* correspondingPort = NULL;
1967  assert(origFU.hasOperationPort(portName));
1968  const FUPort* origPort = origFU.operationPort(portName);
1969  for (int i = 0; i < origFU.operationCount(); i++) {
1970  HWOperation* origOperation = origFU.operation(i);
1971  string opName = origOperation->name();
1972  if (fuToSearch.hasOperation(opName)) {
1973  HWOperation* operation = fuToSearch.operation(opName);
1974  if (!origOperation->isBound(*origPort)) {
1975  continue;
1976  }
1977  int origIO = origOperation->io(*origPort);
1978  FUPort* port = operation->port(origIO);
1979  if (port == NULL) {
1980  throw InstanceNotFound(__FILE__, __LINE__, __func__);
1981  }
1982  if (correspondingPort == NULL) {
1983  correspondingPort = port;
1984  } else if (correspondingPort != port) {
1985  throw InstanceNotFound(__FILE__, __LINE__, __func__);
1986  }
1987  }
1988  }
1989 
1990  if (correspondingPort == NULL) {
1991  THROW_EXCEPTION(InstanceNotFound,
1992  std::string("Corresponding port for [") + portName +
1993  "] defined in HDB was not found in FU of ADF: [" +
1994  fuToSearch.name() + "].");
1995  }
1996 
1997  return *correspondingPort;
1998  }

References __func__, assert, TTAMachine::FunctionUnit::hasOperation(), TTAMachine::FunctionUnit::hasOperationPort(), TTAMachine::HWOperation::io(), TTAMachine::HWOperation::isBound(), TTAMachine::HWOperation::name(), TTAMachine::Component::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), TTAMachine::FunctionUnit::operationPort(), TTAMachine::HWOperation::port(), and THROW_EXCEPTION.

Referenced by addFUToNetlist().

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◆ fuEntry()

FUEntry & ProGe::NetlistGenerator::fuEntry ( const std::string &  fuName) const

Returns the FU entry which was selected to represent the given FU.

Parameters
fuNameName of the FU in ADF.
Returns
The FU entry.
Exceptions
InstanceNotFoundIf the netlist is not created yet or if there was no FU entry for the given FU.

Definition at line 657 of file NetlistGenerator.cc.

657  {
658  try {
659  return *MapTools::valueForKey<FUEntry*>(fuEntryMap_, fuName);
660  } catch (const Exception&) {
661  throw InstanceNotFound(__FILE__, __LINE__, __func__,
662  "Cannot find function unit entry from the netlist.");
663  }
664  }

References __func__, and fuEntryMap_.

Referenced by isParameterizable().

◆ fuGuardPort()

NetlistPort & ProGe::NetlistGenerator::fuGuardPort ( const NetlistPort &  fuPort) const

Returns the guard port of the given FU data port.

Parameters
fuPortThe FU data port.
Returns
The guard port.
Exceptions
InstanceNotFoundIf the netlist does not contain the port.

Definition at line 402 of file NetlistGenerator.cc.

402  {
403  try {
404  return *MapTools::valueForKey<NetlistPort*>(
405  fuGuardPortMap_, &fuPort);
406  } catch (const Exception&) {
407  throw InstanceNotFound(__FILE__, __LINE__, __func__,
408  (boost::format(
409  "Cannot find guard port '%s' in instance name: '%s', "
410  "module name: '%s'") %
411  fuPort.name() % fuPort.parentBlock().instanceName() %
412  fuPort.parentBlock().moduleName())
413  .str());
414  }
415  }

References __func__, fuGuardPortMap_, ProGe::BaseNetlistBlock::instanceName(), ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistPort::name(), and ProGe::NetlistPort::parentBlock().

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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◆ fuOpcodePort()

NetlistPort & ProGe::NetlistGenerator::fuOpcodePort ( const NetlistBlock &  fuBlock) const

Returns the opcode port of the given FU.

Parameters
fuBlockThe FU.
Returns
The opcode port.
Exceptions
InstanceNotFoundIf the given FU does not have an opcode port.

Definition at line 380 of file NetlistGenerator.cc.

380  {
381  try {
382  return *MapTools::valueForKey<NetlistPort*>(
383  fuOpcodePorts_, &fuBlock);
384  } catch (const Exception&) {
385  throw InstanceNotFound(__FILE__, __LINE__, __func__,
386  (boost::format("Cannot find opcode port in function unit "
387  "instance name: '%s',"
388  "module name: '%s'") %
389  fuBlock.instanceName() % fuBlock.moduleName())
390  .str());
391  }
392  }

References __func__, fuOpcodePorts_, ProGe::BaseNetlistBlock::instanceName(), and ProGe::BaseNetlistBlock::moduleName().

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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◆ gcuReturnAddressInPort()

NetlistPort & ProGe::NetlistGenerator::gcuReturnAddressInPort ( ) const

Returns the return address in port of GCU.

Returns
The return address in port.
Exceptions
InstanceNotFoundIf GCU does not have the port.

Definition at line 551 of file NetlistGenerator.cc.

551  {
552  if (raInPort_ != NULL) {
553  return *raInPort_;
554  } else {
555  throw InstanceNotFound(__FILE__, __LINE__, __func__,
556  "Cannot find return address of in port of GCU");
557  }
558  }

References __func__, and raInPort_.

Referenced by DefaultICGenerator::addICToNetlist(), and DefaultICDecoderGenerator::generateDebuggerCode().

◆ gcuReturnAddressOutPort()

NetlistPort & ProGe::NetlistGenerator::gcuReturnAddressOutPort ( ) const

Returns the return address out port of GCU.

Returns
The return address out port.
Exceptions
InstanceNotFoundIf GCU does not have the port.

Definition at line 567 of file NetlistGenerator.cc.

567  {
568  if (raOutPort_ != NULL) {
569  return *raOutPort_;
570  } else {
571  throw InstanceNotFound(__FILE__, __LINE__, __func__,
572  "Cannot find return address of out port of GCU");
573  }
574  }

References __func__, and raOutPort_.

Referenced by DefaultICGenerator::addICToNetlist().

◆ generate()

NetlistBlock * ProGe::NetlistGenerator::generate ( const ProGeOptions &  options,
int  imemWidthInMAUs,
TCEString  entityNameStr = TOPLEVEL_BLOCK_DEFAULT_NAME,
std::ostream &  warningStream = std::cerr 
)

Generates the netlist block of the processor.

Parameters
imemWidthInMAUsWidth of instruction memory in MAUs.
entityNameStrThe name string used to make the netlist blocks uniquely named.
Returns
The newly generated netlist block representing a single TTA Core.
Exceptions
IOExceptionIf some of the HDBs given in IDF cannot be accessed.
InvalidDataIf HDB or IDF is invalid.
OutOfRangeIf the given width of instruction memory is not positive
InstanceNotFoundSomething missing missing from HDB.

Definition at line 188 of file NetlistGenerator.cc.

191  {
192  if (imemWidthInMAUs < 1) {
193  string errorMsg =
194  "Instruction memory width in MAUs must be positive.";
195  throw OutOfRange(__FILE__, __LINE__, __func__, errorMsg);
196  }
197 
198  // add toplevel block
199  coreBlock_ = new NetlistBlock(entityNameStr, "tta_core");
200  coreBlock_->addPackage(context_.coreEntityName() + "_globals");
201  coreBlock_->addPackage(context_.coreEntityName() + "_imem_mau");
202 
203  // add GCU to the netlist
204  addGCUToNetlist(*coreBlock_, imemWidthInMAUs);
205 
206  // add Genrated FUs to the toplevel netlist.
207  for (auto fug : context_.idf().FUGenerations()) {
208  addGeneratableFUsToNetlist(fug, *coreBlock_);
209  }
210 
211  // add function units to the netlist
212  for (int i = 0; i < context_.idf().fuImplementationCount(); i++) {
213  IDF::FUImplementationLocation& location =
214  context_.idf().fuImplementation(i);
215  addFUToNetlist(location, *coreBlock_, warningStream);
216  }
217 
218  // add register files to the netlist
219  for (int i = 0; i < context_.idf().rfImplementationCount(); i++) {
220  RFImplementationLocation& location =
221  context_.idf().rfImplementation(i);
222  addRFToNetlist(options, location, *coreBlock_);
223  }
224 
225  // add immediate units to the netlist
226  for (int i = 0; i < context_.idf().iuImplementationCount(); i++) {
227  RFImplementationLocation& location =
228  context_.idf().iuImplementation(i);
229  addIUToNetlist(options, location, *coreBlock_);
230  }
231 
232  plugin_.completeNetlist(*coreBlock_, *this);
233 
234  return coreBlock_;
235  }

References __func__, addFUToNetlist(), addGCUToNetlist(), addGeneratableFUsToNetlist(), addIUToNetlist(), ProGe::NetlistBlock::addPackage(), addRFToNetlist(), ProGe::ICDecoderGeneratorPlugin::completeNetlist(), context_, coreBlock_, ProGe::ProGeContext::coreEntityName(), IDF::MachineImplementation::FUGenerations(), IDF::MachineImplementation::fuImplementation(), ProGe::ProGeContext::idf(), IDF::MachineImplementation::iuImplementation(), options, plugin_, and IDF::MachineImplementation::rfImplementation().

Referenced by ProGe::ProcessorGenerator::generateProcessor().

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◆ glockPort()

NetlistPort & ProGe::NetlistGenerator::glockPort ( const NetlistBlock &  block) const

Returns the global lock port of the given block in the netlist.

Parameters
blockThe block in the netlist.
Returns
The global lock port of the given block.
Exceptions
InstanceNotFoundIf the netlist does not contain the port.

Definition at line 477 of file NetlistGenerator.cc.

477  {
478  try {
479  return *MapTools::valueForKey<NetlistPort*>(glockPorts_, &block);
480  } catch (const Exception&) {
481  throw InstanceNotFound(__FILE__, __LINE__, __func__,
482  (boost::format("Cannot find global lock port in netlist block "
483  "instance name:"
484  " '%s', module name: '%s'") %
485  block.instanceName() % block.moduleName())
486  .str());
487  }
488  }

References __func__, glockPorts_, ProGe::BaseNetlistBlock::instanceName(), and ProGe::BaseNetlistBlock::moduleName().

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGeneratableFUsToNetlist(), DefaultDecoderGenerator::addGlockPortToDecoder(), and mapGlobalLockPort().

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◆ glockReqPort()

NetlistPort & ProGe::NetlistGenerator::glockReqPort ( const NetlistBlock &  block) const

Returns the global lock request port of the given block in the netlist.

Parameters
blockThe block in the netlist.
Returns
The global lock request port of the given block.
Exceptions
InstanceNotFoundIf the netlist does not contain the port.

Definition at line 510 of file NetlistGenerator.cc.

510  {
511  try {
512  return *MapTools::valueForKey<NetlistPort*>(glockReqPorts_, &block);
513  } catch (const Exception&) {
514  throw InstanceNotFound(__FILE__, __LINE__, __func__,
515  (boost::format("Cannot find global lock request port in "
516  "netlist block "
517  "instance name: '%s', module name: '%s'") %
518  block.instanceName() % block.moduleName())
519  .str());
520  }
521  }

References __func__, glockReqPorts_, ProGe::BaseNetlistBlock::instanceName(), and ProGe::BaseNetlistBlock::moduleName().

Referenced by addFUToNetlist(), addGeneratableFUsToNetlist(), DefaultDecoderGenerator::addLockReqPortToDecoder(), and mapGlobalLockRequestPort().

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◆ hasGlockPort()

bool ProGe::NetlistGenerator::hasGlockPort ( const NetlistBlock &  block) const

Tells whether the given netlist block has a global lock port.

Parameters
blockThe netlist block.
Returns
True if the block has a global lock port, otherwise false.

Definition at line 465 of file NetlistGenerator.cc.

465  {
466  return MapTools::containsKey(glockPorts_, &block);
467  }

References MapTools::containsKey(), and glockPorts_.

Referenced by DefaultDecoderGenerator::addGlockPortToDecoder(), and DefaultDecoderGenerator::glockPortWidth().

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◆ hasGlockReqPort()

bool ProGe::NetlistGenerator::hasGlockReqPort ( const NetlistBlock &  block) const

Tells whether the given netlist block has global lock request port.

Parameters
blockThe netlist block.
Returns
True if the block has a global lock request port, otherwise false.

Definition at line 497 of file NetlistGenerator.cc.

497  {
498  return MapTools::containsKey(glockReqPorts_, &block);
499  }

References MapTools::containsKey(), and glockReqPorts_.

Referenced by DefaultDecoderGenerator::addLockReqPortToDecoder(), and DefaultDecoderGenerator::glockRequestWidth().

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◆ hasOpcodePort()

bool ProGe::NetlistGenerator::hasOpcodePort ( const NetlistPort &  port) const

Returns true if the given RF port has opcode port. Otherwise, returns false.

Definition at line 322 of file NetlistGenerator.cc.

322  {
323  return MapTools::containsKey(rfOpcodePortMap_, &port);
324  }

References MapTools::containsKey(), and rfOpcodePortMap_.

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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◆ immediateUnitWritePort()

NetlistPort & ProGe::NetlistGenerator::immediateUnitWritePort ( const TTAMachine::ImmediateUnit &  iu) const

Returns a netlist port that is the write port of the given immediate unit.

Parameters
iuThe immediate unit.
Returns
The netlist port.
Exceptions
InstanceNotFoundIf the port is not found.

Definition at line 532 of file NetlistGenerator.cc.

533  {
534  try {
535  return *MapTools::valueForKey<NetlistPort*>(iuPortMap_, &iu);
536  } catch (const Exception&) {
537  throw InstanceNotFound(__FILE__, __LINE__, __func__,
538  (boost::format("Cannot find immediate unit '%s' write port.") %
539  iu.name())
540  .str());
541  }
542  }

References __func__, iuPortMap_, and TTAMachine::Component::name().

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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◆ inferLSUSignal()

Signal ProGe::NetlistGenerator::inferLSUSignal ( const std::string &  portName)
staticprivate

Definition at line 2151 of file NetlistGenerator.cc.

2151  {
2152  size_t pos = 0;
2153  if (((pos = portName.find("addr")) != std::string::npos)) {
2154  return SignalType::ADDRESS;
2155  } else if (((pos = portName.find("data")) != std::string::npos)) {
2156  if ((portName.find("_in", pos + 4)) != std::string::npos) {
2157  return SignalType::READ_DATA;
2158  } else if ((portName.find("_out", pos + 4)) != std::string::npos) {
2159  return SignalType::WRITE_DATA;
2160  }
2161  } else if (((pos = portName.find("mem_en")) != std::string::npos)) {
2162  if ((portName.find("_x", pos + 6)) != std::string::npos) {
2163  return Signal(SignalType::READ_WRITE_REQUEST, ActiveState::LOW);
2164  } else {
2165  return SignalType::READ_WRITE_REQUEST;
2166  }
2167  } else if (((pos = portName.find("wr_mask")) != std::string::npos)) {
2168  if ((portName.find("_x", pos + 7)) != std::string::npos) {
2169  return Signal(SignalType::WRITE_BITMASK, ActiveState::LOW);
2170  } else {
2171  return SignalType::WRITE_BITMASK;
2172  }
2173  } else if (((pos = portName.find("wr_en")) != std::string::npos)) {
2174  if ((portName.find("_x", pos + 5)) != std::string::npos) {
2175  return Signal(SignalType::WRITEMODE, ActiveState::LOW);
2176  } else {
2177  return SignalType::WRITEMODE;
2178  }
2179  }
2180  return SignalType::UNDEFINED;
2181  }

References ProGe::ADDRESS, ProGe::LOW, ProGe::READ_DATA, ProGe::READ_WRITE_REQUEST, ProGe::UNDEFINED, ProGe::WRITE_BITMASK, ProGe::WRITE_DATA, and ProGe::WRITEMODE.

Referenced by addFUExternalPortsToNetlist().

◆ instructionDecoder()

NetlistBlock & ProGe::NetlistGenerator::instructionDecoder ( ) const

Returns the instruction decoder block in the netlist.

Returns
The instruction decoder block.
Exceptions
InstanceNotFoundIf there is no instruction decoder in the netlist.

Definition at line 600 of file NetlistGenerator.cc.

600  {
601  if (instructionDecoder_ == NULL) {
602  throw InstanceNotFound(__FILE__, __LINE__, __func__,
603  "Cannot find instruction decoder block from the netlist.");
604  } else {
605  return *instructionDecoder_;
606  }
607  }

References __func__, and instructionDecoder_.

Referenced by DefaultICDecoderGenerator::addRV32MicroCode(), DefaultDecoderGenerator::completeDecoderBlock(), DefaultICDecoderGenerator::generateDebuggerCode(), and DefaultDecoderGenerator::opcodeWidth().

◆ instructionDecompressor()

NetlistBlock & ProGe::NetlistGenerator::instructionDecompressor ( ) const

Returns the instruction decompressor block in the netlist.

Returns
The instruction decompressor block.
Exceptions
InstanceNotFoundIf there is no instruction decompressor in the netlist.

Definition at line 636 of file NetlistGenerator.cc.

636  {
637  if (instructionDecompressor_ == NULL) {
638  throw InstanceNotFound(__FILE__, __LINE__, __func__,
639  "Cannot find instruction decompressor block from the "
640  "netlist.");
641  } else {
642  return *instructionDecompressor_;
643  }
644  }

References __func__, and instructionDecompressor_.

Referenced by DefaultICDecoderGenerator::addRV32MicroCode().

◆ instructionFetch()

NetlistBlock & ProGe::NetlistGenerator::instructionFetch ( ) const

Returns the instruction fetch block in the netlist.

Returns
The instruction fetch block.
Exceptions
InstanceNotFoundIf there is no instruction fetch in the netlist.

Definition at line 617 of file NetlistGenerator.cc.

617  {
618  if (instructionFetch_ == NULL) {
619  throw InstanceNotFound(__FILE__, __LINE__, __func__,
620  "Cannot find instruction fetch block from the netlist.");
621  } else {
622  return *instructionFetch_;
623  }
624  }

References __func__, and instructionFetch_.

Referenced by DefaultICDecoderGenerator::addDummyIfetchDebugPorts(), DefaultICDecoderGenerator::addInstructioRegisterBypass(), DefaultICDecoderGenerator::addRV32MicroCode(), DefaultICDecoderGenerator::generate(), and DefaultICDecoderGenerator::generateDebuggerCode().

◆ instructionMemory()

TTAMachine::AddressSpace & ProGe::NetlistGenerator::instructionMemory ( const TTAMachine::Machine &  machine)
staticprivate

Returns the address space that represents the instruction memory of the given machine.

Parameters
machineThe machine.
Returns
The address space.
Exceptions
IllegalMachineIf the machine does not have the instruction memory address space.

Definition at line 2041 of file NetlistGenerator.cc.

2041  {
2042  ControlUnit* cu = machine.controlUnit();
2043  if (cu == NULL) {
2044  string errorMsg = "The machine does not have a control unit.";
2045  throw IllegalMachine(__FILE__, __LINE__, __func__, errorMsg);
2046  }
2047 
2048  AddressSpace* iMem = cu->addressSpace();
2049  if (iMem == NULL) {
2050  string errorMsg =
2051  "The control unit does not have an address space.";
2052  throw IllegalMachine(__FILE__, __LINE__, __func__, errorMsg);
2053  }
2054 
2055  return *iMem;
2056  }

References __func__, TTAMachine::FunctionUnit::addressSpace(), TTAMachine::Machine::controlUnit(), and machine.

Referenced by instructionMemoryAddressWidth(), and instructionMemoryWidth().

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◆ instructionMemoryAddressWidth()

int ProGe::NetlistGenerator::instructionMemoryAddressWidth ( const TTAMachine::Machine &  machine)
staticprivate

Explores the given machine for the width of the instruction memory address.

Parameters
machineThe machine.
Returns
The width of the instruction memory address.
Exceptions
IllegalMachineIf the machine is erroneous.

Definition at line 2009 of file NetlistGenerator.cc.

2010  {
2011  AddressSpace& iMem = instructionMemory(machine);
2012  return MathTools::requiredBits(iMem.end());
2013  }

References TTAMachine::AddressSpace::end(), instructionMemory(), machine, and MathTools::requiredBits().

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◆ instructionMemoryWidth()

int ProGe::NetlistGenerator::instructionMemoryWidth ( const TTAMachine::Machine &  machine)
staticprivate

Explores the given machine for the width of the instruction memory.

Parameters
machineThe machine.
Returns
The width of the instruction memory.
Exceptions
IllegalMachineIf the machine is erroneous.

Definition at line 2023 of file NetlistGenerator.cc.

2024  {
2025  AddressSpace& iMem = instructionMemory(machine);
2026  return iMem.width();
2027  }

References instructionMemory(), machine, and TTAMachine::AddressSpace::width().

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◆ isLSU()

bool ProGe::NetlistGenerator::isLSU ( const TTAMachine::FunctionUnit &  fu) const
private

(Ugly) heursitics for identifying an LSU.

If it has an address space and implements a memory operation, it is an LSU

Parameters
fuFunction unit to be tested
Returns
Is the fu an LSU

Definition at line 2102 of file NetlistGenerator.cc.

2102  {
2103 
2104  if (!fu.hasAddressSpace()) {
2105  return false;
2106  }
2107 
2108  const int opCount = 18;
2109  TCEString ops[opCount] = {
2110  "ldw", "ldh", "ldq", "ldw2", "ldw4",
2111  "stw", "sth", "stq", "stw2", "stw4",
2112  "ld8", "ldu8", "ld16","ldu16", "ld32",
2113  "st8", "st16", "st32"
2114  };
2115 
2116  for (auto& op : ops) {
2117  if (fu.hasOperationLowercase(op)) {
2118  return true;
2119  }
2120  }
2121  return false;
2122  }

References TTAMachine::FunctionUnit::hasAddressSpace(), and TTAMachine::FunctionUnit::hasOperationLowercase().

Referenced by addFUToNetlist().

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◆ isLSUDataPort()

bool ProGe::NetlistGenerator::isLSUDataPort ( const TTAMachine::FunctionUnit &  adfFU,
const std::string &  portName 
)
staticprivate

(Ugly) heuristics for identifying an LSU data memory port.

The identification is made by partial match of the port's name.

Parameters
portNameThe port name given in HDB.
Returns
True if the port is LSU data memory port.

Definition at line 2132 of file NetlistGenerator.cc.

2133  {
2134 
2135  if (!adfFU.hasAddressSpace()) {
2136  return false;
2137  }
2138 
2139  static const std::set<std::string> magicWords{
2140  "addr", "data", "mem_en", "wr_en", "wr_mask"};
2141 
2142  for (auto magicWord : magicWords) {
2143  if (portName.find(magicWord) != std::string::npos) {
2144  return true;
2145  }
2146  }
2147 
2148  return false;
2149  }

References TTAMachine::FunctionUnit::hasAddressSpace().

Referenced by addFUExternalPortsToNetlist().

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◆ isParameterizable()

bool ProGe::NetlistGenerator::isParameterizable ( const std::string &  paramName,
const HDB::FUEntry *  fuEntry 
) const
private

Checks if the given parameter is defined parametrizable in the given FUImplementation

Parameters
paramNameName of the parameter
fuImplementationFUImplementation to be tested

Definition at line 1832 of file NetlistGenerator.cc.

1833  {
1834  FUImplementation& fuImplementation = fuEntry->implementation();
1835 
1836  for (int i = 0; i < fuImplementation.architecturePortCount(); i++) {
1837 
1838  FUPortImplementation& port = fuImplementation.architecturePort(i);
1839  string widthFormula = port.widthFormula();
1840  if (widthFormula == paramName) {
1841  return fuEntry->architecture().hasParameterizedWidth(
1842  port.architecturePort());
1843  }
1844  }
1845  return false;
1846  }

References HDB::FUEntry::architecture(), HDB::FUPortImplementation::architecturePort(), HDB::FUImplementation::architecturePort(), HDB::FUImplementation::architecturePortCount(), fuEntry(), HDB::FUArchitecture::hasParameterizedWidth(), HDB::FUEntry::implementation(), and HDB::FUPortImplementation::widthFormula().

Referenced by addFUToNetlist().

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◆ loadPort()

NetlistPort & ProGe::NetlistGenerator::loadPort ( const NetlistPort &  port) const

Returns the load enable port of the given port in the netlist.

Parameters
portThe architectural port in the netlist.
Returns
The load enable port of the given port.
Exceptions
InstanceNotFoundIf the netlist does not contain the port.

Definition at line 304 of file NetlistGenerator.cc.

304  {
305  try {
306  return *MapTools::valueForKey<NetlistPort*>(loadPortMap_, &port);
307  } catch (const Exception&) {
308  throw InstanceNotFound(__FILE__, __LINE__, __func__,
309  (boost::format(
310  "Cannot find load port '%s' in instance name: '%s', "
311  "module name: '%s'") %
312  port.name() % port.parentBlock().instanceName() %
313  port.parentBlock().moduleName())
314  .str());
315  }
316  }

References __func__, ProGe::BaseNetlistBlock::instanceName(), loadPortMap_, ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistPort::name(), and ProGe::NetlistPort::parentBlock().

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), DefaultDecoderGenerator::completeDecoderBlock(), and mapLoadPort().

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◆ mapClockPort()

void ProGe::NetlistGenerator::mapClockPort ( const NetlistBlock &  block,
NetlistPort &  clkPort 
)
private

Maps the given clock port for the given block.

Parameters
blockThe netlist block.
clkPortThe clock port of the block.

Definition at line 1733 of file NetlistGenerator.cc.

1734  {
1735 
1736  assert(!MapTools::containsKey(clkPorts_, &block));
1737  clkPorts_.insert(
1738  std::pair<const NetlistBlock*, NetlistPort*>(&block, &clkPort));
1739  }

References assert, clkPort(), clkPorts_, and MapTools::containsKey().

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), and addGeneratableFUsToNetlist().

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◆ mapFUGuardPort()

void ProGe::NetlistGenerator::mapFUGuardPort ( const NetlistPort &  dataPort,
NetlistPort &  guardPort 
)
private

Maps the given guard port for the given FU data port.

Parameters
dataPortThe data port.
guardPortThe guard port.

Definition at line 1803 of file NetlistGenerator.cc.

1804  {
1805 
1806  assert(!MapTools::containsKey(fuGuardPortMap_, &dataPort));
1807  fuGuardPortMap_.insert(
1808  std::pair<const NetlistPort*, NetlistPort*>(&dataPort, &guardPort));
1809  }

References assert, MapTools::containsKey(), and fuGuardPortMap_.

Referenced by addFUToNetlist().

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◆ mapFUOpcodePort()

void ProGe::NetlistGenerator::mapFUOpcodePort ( const NetlistBlock &  block,
NetlistPort &  port 
)
private

Maps the given opcode port for the given FU block.

Parameters
blockThe FU block.
opcodePortThe opcode port of the FU block.

Definition at line 1719 of file NetlistGenerator.cc.

1720  {
1721 
1722  assert(!MapTools::containsKey(fuOpcodePorts_, &block));
1723  fuOpcodePorts_.insert(
1724  std::pair<const NetlistBlock*, NetlistPort*>(&block, &port));
1725  }

References assert, MapTools::containsKey(), and fuOpcodePorts_.

Referenced by addFUToNetlist(), and addGeneratableFUsToNetlist().

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◆ mapGlobalLockPort()

void ProGe::NetlistGenerator::mapGlobalLockPort ( const NetlistBlock &  block,
NetlistPort &  glockPort 
)
private

Maps the given global lock port for the given block.

Parameters
blockThe netlist block.
glockPortThe global lock port of the block.

Definition at line 1761 of file NetlistGenerator.cc.

1762  {
1763 
1764  assert(!MapTools::containsKey(glockPorts_, &block));
1765  glockPorts_.insert(
1766  std::pair<const NetlistBlock*, NetlistPort*>(&block, &glockPort));
1767  }

References assert, MapTools::containsKey(), glockPort(), and glockPorts_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), and addGeneratableFUsToNetlist().

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◆ mapGlobalLockRequestPort()

void ProGe::NetlistGenerator::mapGlobalLockRequestPort ( const NetlistBlock &  block,
NetlistPort &  glockReqPort 
)

Maps the given global lock request port for the given block.

Parameters
blockThe netlist block.
glockReqPortThe global lock request port of the block.

Definition at line 1775 of file NetlistGenerator.cc.

1776  {
1777 
1778  assert(!MapTools::containsKey(glockReqPorts_, &block));
1779  glockReqPorts_.insert(std::pair<const NetlistBlock*, NetlistPort*>(
1780  &block, &glockReqPort));
1781  }

References assert, MapTools::containsKey(), glockReqPort(), and glockReqPorts_.

Referenced by addFUToNetlist(), and addGeneratableFUsToNetlist().

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◆ mapImmediateUnitWritePort()

void ProGe::NetlistGenerator::mapImmediateUnitWritePort ( const TTAMachine::ImmediateUnit &  iu,
NetlistPort &  port 
)
private

Maps the given netlist port as a write port of the given immediate unit.

Parameters
iuThe immediate unit.
portThe netlist port.

Definition at line 1818 of file NetlistGenerator.cc.

1819  {
1820 
1821  iuPortMap_.insert(
1822  std::pair<const ImmediateUnit*, NetlistPort*>(&iu, &port));
1823  }

References iuPortMap_.

Referenced by addBaseRFToNetlist().

◆ mapLoadPort()

void ProGe::NetlistGenerator::mapLoadPort ( const NetlistPort &  port,
NetlistPort &  loadPort 
)
private

Maps the given load port for the given architectural port.

Parameters
portThe architectural port in the netlist.
loadPortThe load port of the architectural port.

Definition at line 1691 of file NetlistGenerator.cc.

1692  {
1693 
1694  assert(!MapTools::containsKey(loadPortMap_, &port));
1695  loadPortMap_.insert(
1696  std::pair<const NetlistPort*, NetlistPort*>(&port, &loadPort));
1697  }

References assert, MapTools::containsKey(), loadPort(), and loadPortMap_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), and ProGe::GeneratableFUNetlistBlock::addInOperand().

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◆ mapNetlistBlock()

void ProGe::NetlistGenerator::mapNetlistBlock ( const TTAMachine::Unit &  unit,
NetlistBlock &  netlistBlock 
)
private

Maps the given ADF Function Unit to the given netlist block.

Parameters
adfFUThe Function Unit in ADF (Machine Object Model).
netlistBlockThe corresponding block in the netlist.

Definition at line 1668 of file NetlistGenerator.cc.

1669  {
1670  assert(!MapTools::containsKey(unitCorrespondenceMap_, &unit));
1671  unitCorrespondenceMap_.insert(
1672  std::pair<const Unit*, NetlistBlock*>(&unit, &netlistBlock));
1673  }

References assert, MapTools::containsKey(), netlistBlock(), and unitCorrespondenceMap_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), and addGeneratableFUsToNetlist().

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◆ mapNetlistPort()

void ProGe::NetlistGenerator::mapNetlistPort ( const TTAMachine::Port &  adfPort,
NetlistPort &  netlistPort 
)
private

Maps the given ADF port to the given netlist port.

Parameters
adfPortThe port in ADF (Machine Object Model).
netlistPortThe corresponding port in the netlist.

Definition at line 1650 of file NetlistGenerator.cc.

1651  {
1652 
1653  if (portCorrespondenceMap_.count(&adfPort) != 0) {
1654  auto range = portCorrespondenceMap_.equal_range(&adfPort);
1655  for (auto i = range.first; i != range.second; ++i) {
1656  assert(i->second->direction() != netlistPort.direction());
1657  }
1658  }
1659  portCorrespondenceMap_.emplace(&adfPort, &netlistPort);
1660  }

References assert, ProGe::NetlistPort::direction(), netlistPort(), and portCorrespondenceMap_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), ProGe::GeneratableFUNetlistBlock::addInOperand(), and ProGe::GeneratableFUNetlistBlock::addOutOperand().

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◆ mapResetPort()

void ProGe::NetlistGenerator::mapResetPort ( const NetlistBlock &  block,
NetlistPort &  resetPort 
)
private

Maps the given reset port for the given block.

Parameters
blockThe netlist block.
resetPortThe reset port of the block.

Definition at line 1747 of file NetlistGenerator.cc.

1748  {
1749 
1750  assert(!MapTools::containsKey(rstPorts_, &block));
1751  rstPorts_.insert(
1752  std::pair<const NetlistBlock*, NetlistPort*>(&block, &resetPort));
1753  }

References assert, MapTools::containsKey(), and rstPorts_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), and addGeneratableFUsToNetlist().

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◆ mapRFGuardPort()

void ProGe::NetlistGenerator::mapRFGuardPort ( const NetlistBlock &  block,
NetlistPort &  guardPort 
)
private

Maps the given guard port for the given RF block.

Parameters
blockThe netlist block.
guardPortThe guard port of the block.

Definition at line 1789 of file NetlistGenerator.cc.

1790  {
1791 
1792  assert(!MapTools::containsKey(rfGuardPorts_, &block));
1793  rfGuardPorts_.insert(
1794  std::pair<const NetlistBlock*, NetlistPort*>(&block, &guardPort));
1795  }

References assert, MapTools::containsKey(), and rfGuardPorts_.

Referenced by addBaseRFToNetlist().

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◆ mapRFOpcodePort()

void ProGe::NetlistGenerator::mapRFOpcodePort ( const NetlistPort &  port,
NetlistPort &  opcodePort 
)
private

Maps the given opcode port for the given architectural RF port.

Parameters
portThe architectural port in the netlist.
opcodePortThe opcode port of the architectural port.

Definition at line 1705 of file NetlistGenerator.cc.

1706  {
1707 
1708  assert(!MapTools::containsKey(rfOpcodePortMap_, &port));
1709  rfOpcodePortMap_.insert(
1710  std::pair<const NetlistPort*, NetlistPort*>(&port, &opcodePort));
1711  }

References assert, MapTools::containsKey(), and rfOpcodePortMap_.

Referenced by addBaseRFToNetlist().

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◆ netlistBlock()

NetlistBlock & ProGe::NetlistGenerator::netlistBlock ( const TTAMachine::Unit &  unit) const

Returns the netlist block which is corresponding to the given unit in the machine object model.

Parameters
unitThe Unit in the machine object model
Returns
The corresponding block in the netlist.
Exceptions
InstanceNotFoundIf the netlist does not contain the block.

Definition at line 283 of file NetlistGenerator.cc.

283  {
284  try {
285  return *MapTools::valueForKey<NetlistBlock*>(
286  unitCorrespondenceMap_, &unit);
287  } catch (const Exception&) {
288  throw InstanceNotFound(__FILE__, __LINE__, __func__,
289  (boost::format(
290  "Cannot find corresponding netlist block for '%s'") %
291  unit.name())
292  .str());
293  }
294  }

References __func__, TTAMachine::Component::name(), and unitCorrespondenceMap_.

Referenced by DefaultDecoderGenerator::addGlockPortToDecoder(), addIUToNetlist(), DefaultDecoderGenerator::addLockReqPortToDecoder(), addRFToNetlist(), DefaultDecoderGenerator::completeDecoderBlock(), DefaultDecoderGenerator::glockPortWidth(), DefaultDecoderGenerator::glockRequestWidth(), and mapNetlistBlock().

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◆ netlistPort()

NetlistPort & ProGe::NetlistGenerator::netlistPort ( const TTAMachine::Port &  port,
Direction  dir = IN 
) const

Returns the netlist port which is corresponding to the given port in the machine object model.

Parameters
portThe port in the machine object model
Returns
The corresponding port in the netlist.
Exceptions
InstanceNotFoundIf the netlist does not contain the port.

Definition at line 247 of file NetlistGenerator.cc.

248  {
249  if (portCorrespondenceMap_.count(&port) > 0) {
250  // Override direction with port direction if the port is
251  // unidirectional
252  if (!(port.isInput() && port.isOutput())) {
253  dir = port.isInput() ? IN : OUT;
254  }
255 
256  auto range = portCorrespondenceMap_.equal_range(&port);
257  for (auto i = range.first; i != range.second; ++i) {
258  if(i->second->direction() == dir)
259  return *i->second;
260  }
261  return *MapTools::valueForKey<NetlistPort*>(
262  portCorrespondenceMap_, &port);
263  }
264 
265  throw InstanceNotFound(__FILE__, __LINE__, __func__,
266  (boost::format(
267  "Cannot find netlist port '%s' in parent unit: '%s'") %
268  port.name() % port.parentUnit()->name())
269  .str());
270  }

References __func__, ProGe::IN, TTAMachine::Port::isInput(), TTAMachine::Port::isOutput(), TTAMachine::Port::name(), TTAMachine::Component::name(), ProGe::OUT, TTAMachine::Port::parentUnit(), and portCorrespondenceMap_.

Referenced by DefaultICGenerator::addICToNetlist(), DefaultDecoderGenerator::completeDecoderBlock(), and mapNetlistPort().

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◆ netlistPortIsMapped()

bool ProGe::NetlistGenerator::netlistPortIsMapped ( const TTAMachine::Port &  adfPort)
private

Returns true if the given ADF port is mapped to some netlist port.

Parameters
adfPortThe port in ADF (Machine Object Model).

Definition at line 1681 of file NetlistGenerator.cc.

1681  {
1682  return portCorrespondenceMap_.count(&adfPort) != 0;
1683  }

References portCorrespondenceMap_.

Referenced by addGCUToNetlist().

◆ opcodePortWidth() [1/2]

int ProGe::NetlistGenerator::opcodePortWidth ( const HDB::FUEntry &  fu,
std::ostream &  warningStream 
)
staticprivate

Calculates the required opcode port width for the given FU.

Parameters
fuThe FU.
warningStreamOutput stream where warnings are written
Returns
The required width of opcode port.
Exceptions
InvalidDataIf the HDB is missing some information.

Definition at line 1889 of file NetlistGenerator.cc.

1890  {
1891  assert(fu.hasImplementation());
1892  assert(fu.hasArchitecture());
1893  FUImplementation& implementation = fu.implementation();
1894  FunctionUnit& architecture = fu.architecture().architecture();
1895  int portWidth = 0;
1896 
1897  // operation codes are now numbered according to their alphabetical
1898  // order
1899  set<string> opcodeSet;
1900  for (int i = 0; i < architecture.operationCount(); i++) {
1901  HWOperation* operation = architecture.operation(i);
1902  opcodeSet.insert(operation->name());
1903  }
1904 
1905  int opcode = 0;
1906  for (set<string>::iterator iter = opcodeSet.begin();
1907  iter != opcodeSet.end(); iter++) {
1908  // there is an old opcode value in hdb
1909  if (opcodeSet.size() != 1 && implementation.hasOpcode(*iter)) {
1910  // old value differs from current guide line
1911  if (opcode != implementation.opcode(*iter)) {
1912  warningStream << "Warning: Opcode defined in HDB for "
1913  << "operation " << *iter
1914  << " does not comply with the requirement "
1915  << "for numbering the operation codes "
1916  << "according to alphabetical order of "
1917  << "operations. Please fix the vhdl and "
1918  << "hdb entry." << std::endl;
1919  }
1920  }
1921  int requiredBits = MathTools::requiredBits(opcode);
1922  if (requiredBits > portWidth) {
1923  portWidth = requiredBits;
1924  }
1925  opcode++;
1926  }
1927 
1928  return portWidth;
1929  }

References HDB::FUEntry::architecture(), HDB::FUArchitecture::architecture(), assert, HDB::FUEntry::hasArchitecture(), HDB::FUEntry::hasImplementation(), HDB::FUEntry::implementation(), implementation, TTAMachine::HWOperation::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), and MathTools::requiredBits().

Referenced by addFUToNetlist(), and addGCUToNetlist().

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◆ opcodePortWidth() [2/2]

int ProGe::NetlistGenerator::opcodePortWidth ( const TTAMachine::ControlUnit &  gcu)
staticprivate

Calculates the required opcode port width for the given GCU.

Parameters
gcuThe GCU.
Returns
The required width of opcode port.

Definition at line 1937 of file NetlistGenerator.cc.

1937  {
1938  set<string> opcodeSet;
1939  for (int i = 0; i < gcu.operationCount(); i++) {
1940  HWOperation* operation = gcu.operation(i);
1941  opcodeSet.insert(operation->name());
1942  }
1943 
1944  // Assumes that operations of GCU are coded as
1945  // 0..operationCount()-1.
1946  if (opcodeSet.size() < 2) {
1947  return 1;
1948  } else {
1949  return MathTools::requiredBits(opcodeSet.size() - 1);
1950  }
1951  }

References TTAMachine::HWOperation::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), and MathTools::requiredBits().

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◆ rfEntry()

HDB::RFEntry & ProGe::NetlistGenerator::rfEntry ( const std::string &  rfName) const

Returns the RF entry which was selected to represent the given RF.

Parameters
fuNameName of the RF in ADF.
Returns
The RF entry.
Exceptions
InstanceNotFoundIf the netlist is not created yet or if there was no RF entry for the given RF.

Definition at line 676 of file NetlistGenerator.cc.

676  {
677  try {
678  return *MapTools::valueForKey<RFEntry*>(rfEntryMap_, rfName);
679  } catch (const Exception&) {
680  throw InstanceNotFound(__FILE__, __LINE__, __func__,
681  "Cannot find register file entry from the netlist.");
682  }
683  }

References __func__, and rfEntryMap_.

Referenced by DefaultDecoderGenerator::sacEnabled().

◆ rfGuardPort()

NetlistPort & ProGe::NetlistGenerator::rfGuardPort ( const NetlistBlock &  rfBlock) const

Returns the guard port of the given RF block in the netlist.

Parameters
rfBlockThe RF block in the netlist.
Returns
The guard port of the given block.
Exceptions
InstanceNotFoundIf the netlist does not contain the port.

Definition at line 357 of file NetlistGenerator.cc.

357  {
358  try {
359  return *MapTools::valueForKey<NetlistPort*>(
360  rfGuardPorts_, &rfBlock);
361  } catch (const Exception&) {
362  throw InstanceNotFound(__FILE__, __LINE__, __func__,
363  (boost::format("Cannot find guard port in register file "
364  "instance name: '%s',"
365  "module name: '%s'") %
366  rfBlock.instanceName() % rfBlock.moduleName())
367  .str());
368  }
369  }

References __func__, ProGe::BaseNetlistBlock::instanceName(), ProGe::BaseNetlistBlock::moduleName(), and rfGuardPorts_.

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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◆ rfOpcodePort()

NetlistPort & ProGe::NetlistGenerator::rfOpcodePort ( const NetlistPort &  port) const

Returns the opcode port of the given RF port in the netlist.

Parameters
portThe architectural RF port in the netlist.
Returns
The opcode port of the given port.
Exceptions
InstanceNotFoundIf the netlist does not contain the port.

Definition at line 334 of file NetlistGenerator.cc.

334  {
335  try {
336  return *MapTools::valueForKey<NetlistPort*>(
337  rfOpcodePortMap_, &port);
338  } catch (const Exception&) {
339  throw InstanceNotFound(__FILE__, __LINE__, __func__,
340  (boost::format("Cannot find rf opcode port '%s' in "
341  "instance name: '%s', "
342  "module name: '%s'") %
343  port.name() % port.parentBlock().instanceName() %
344  port.parentBlock().moduleName())
345  .str());
346  }
347  }

References __func__, ProGe::BaseNetlistBlock::instanceName(), ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistPort::name(), ProGe::NetlistPort::parentBlock(), and rfOpcodePortMap_.

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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◆ rstPort()

NetlistPort & ProGe::NetlistGenerator::rstPort ( const NetlistBlock &  block) const

Returns the reset port of the given block in the netlist.

Parameters
blockThe block in the netlist.
Returns
The reset port of the given block.
Exceptions
InstanceNotFoundIf the netlist does not contain the port.

Definition at line 446 of file NetlistGenerator.cc.

446  {
447  try {
448  return *MapTools::valueForKey<NetlistPort*>(rstPorts_, &block);
449  } catch (const Exception&) {
450  throw InstanceNotFound(__FILE__, __LINE__, __func__,
451  (boost::format("Cannot find reset port in netlist block "
452  "instance name: "
453  "'%s', module name: '%s'") %
454  block.instanceName() % block.moduleName())
455  .str());
456  }
457  }

References __func__, ProGe::BaseNetlistBlock::instanceName(), ProGe::BaseNetlistBlock::moduleName(), and rstPorts_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGeneratableFUsToNetlist(), DefaultICDecoderGenerator::addRV32MicroCode(), and DefaultICDecoderGenerator::generateDebuggerCode().

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◆ translateDirection()

ProGe::Direction ProGe::NetlistGenerator::translateDirection ( HDB::Direction  direction)
staticprivate

Definition at line 2059 of file NetlistGenerator.cc.

2059  {
2060  switch (direction) {
2061  case HDB::IN:
2062  return IN;
2063  case HDB::OUT:
2064  return OUT;
2065  case HDB::BIDIR:
2066  return BIDIR;
2067  default:
2068  assert(false && "Unknown HDB::direction.");
2069  return IN;
2070  }
2071  }

References assert, HDB::BIDIR, ProGe::BIDIR, HDB::IN, ProGe::IN, HDB::OUT, and ProGe::OUT.

Referenced by addBaseRFToNetlist(), addFUExternalPortsToNetlist(), and addFUToNetlist().

◆ ttaCore()

NetlistBlock & ProGe::NetlistGenerator::ttaCore ( ) const

Returns the TTA core block in the netlist.

Returns
The TTA core block.
Exceptions
InstanceNotFoundIf there is no instruction decoder in the netlist.

Definition at line 584 of file NetlistGenerator.cc.

584  {
585  if (coreBlock_ == NULL) {
586  throw InstanceNotFound(__FILE__, __LINE__, __func__,
587  "Cannot find TTA core block from the netlist.");
588  }
589  return *coreBlock_;
590  }

References __func__, and coreBlock_.

Friends And Related Function Documentation

◆ GeneratableFUNetlistBlock

friend class GeneratableFUNetlistBlock
friend

Definition at line 85 of file NetlistGenerator.hh.

Referenced by addGeneratableFUsToNetlist().

Member Data Documentation

◆ ADDR_WIDTH

const std::string ProGe::NetlistGenerator::ADDR_WIDTH
static

Definition at line 152 of file NetlistGenerator.hh.

◆ clkPorts_

PortPurposeMap ProGe::NetlistGenerator::clkPorts_
private

Maps clock ports.

Definition at line 258 of file NetlistGenerator.hh.

Referenced by clkPort(), and mapClockPort().

◆ context_

const ProGeContext& ProGe::NetlistGenerator::context_
private

Definition at line 246 of file NetlistGenerator.hh.

Referenced by addFUToNetlist(), addGCUToNetlist(), addGeneratableFUsToNetlist(), addIUToNetlist(), addRFToNetlist(), context(), and generate().

◆ coreBlock_

NetlistBlock* ProGe::NetlistGenerator::coreBlock_
private

The TTA core block.

Definition at line 274 of file NetlistGenerator.hh.

Referenced by generate(), and ttaCore().

◆ DECODER_CLOCK_PORT

const std::string ProGe::NetlistGenerator::DECODER_CLOCK_PORT = CLOCK_PORT_NAME
static

Clock port name in instruction decoder.

Definition at line 132 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ DECODER_INSTR_WORD_PORT

const std::string ProGe::NetlistGenerator::DECODER_INSTR_WORD_PORT
static
Initial value:
=
INSTRUCTIONWORD_PORT_NAME

Instruction word port name in instruction decoder.

Definition at line 128 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ DECODER_LOCK_REQ_IN_PORT

const std::string ProGe::NetlistGenerator::DECODER_LOCK_REQ_IN_PORT
static
Initial value:
=
LOCK_PORT_NAME

Lock request in port name in instruction decoder.

Definition at line 142 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ DECODER_LOCK_REQ_OUT_PORT

const std::string ProGe::NetlistGenerator::DECODER_LOCK_REQ_OUT_PORT
static
Initial value:
=
LOCK_REQUEST_PORT_NAME

Lock request out port name in instruction decoder.

Definition at line 140 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ DECODER_LOCK_STATUS_PORT

const std::string ProGe::NetlistGenerator::DECODER_LOCK_STATUS_PORT
static
Initial value:
=
LOCK_STATUS_PORT_NAME

Definition at line 144 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ DECODER_PC_LOAD_PORT

const std::string ProGe::NetlistGenerator::DECODER_PC_LOAD_PORT
static
Initial value:
=
PC_LOAD_PORT_NAME

PC load port name in instruction decoder.

Definition at line 136 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ DECODER_PC_OPCODE_PORT

const std::string ProGe::NetlistGenerator::DECODER_PC_OPCODE_PORT
static
Initial value:
=
PC_OPCODE_PORT_NAME

PC opcode port name in instruction decoder.

Definition at line 138 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ DECODER_RA_LOAD_PORT

const std::string ProGe::NetlistGenerator::DECODER_RA_LOAD_PORT
static
Initial value:
=
RA_LOAD_PORT_NAME

RA load port name in instruction decoder.

Definition at line 134 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ DECODER_RESET_PORT

const std::string ProGe::NetlistGenerator::DECODER_RESET_PORT = RESET_PORT_NAME
static

Reset port name in instruction decoder.

Definition at line 130 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ DECOMP_GLOCK_PORT

const std::string ProGe::NetlistGenerator::DECOMP_GLOCK_PORT
static
Initial value:
=
GLOBAL_LOCK_PORT_NAME

Global lock out port name in decompressor.

Definition at line 148 of file NetlistGenerator.hh.

◆ DECOMP_INSTR_WORD_PORT

const std::string ProGe::NetlistGenerator::DECOMP_INSTR_WORD_PORT
static
Initial value:
=
INSTRUCTIONWORD_PORT_NAME

Instruction word port name in decompressor.

Definition at line 150 of file NetlistGenerator.hh.

◆ DECOMP_LOCK_REQ_IN_PORT

const std::string ProGe::NetlistGenerator::DECOMP_LOCK_REQ_IN_PORT
static
Initial value:
=
LOCK_REQUEST_PORT_NAME

Lock request in port name in decompressor.

Definition at line 146 of file NetlistGenerator.hh.

◆ FETCHBLOCK_PORT_NAME

const std::string ProGe::NetlistGenerator::FETCHBLOCK_PORT_NAME = "fetchblock"
static

Definition at line 154 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist().

◆ fuEntryMap_

FUEntryMap ProGe::NetlistGenerator::fuEntryMap_
private

Maps FU implementations for different FU's.

Definition at line 282 of file NetlistGenerator.hh.

Referenced by addFUToNetlist(), fuEntry(), and ~NetlistGenerator().

◆ fuGuardPortMap_

PortRelationMap ProGe::NetlistGenerator::fuGuardPortMap_
private

Maps FU guard ports.

Definition at line 268 of file NetlistGenerator.hh.

Referenced by fuGuardPort(), and mapFUGuardPort().

◆ fuOpcodePorts_

PortPurposeMap ProGe::NetlistGenerator::fuOpcodePorts_
private

Maps FU opcode ports.

Definition at line 270 of file NetlistGenerator.hh.

Referenced by fuOpcodePort(), and mapFUOpcodePort().

◆ glockPorts_

PortPurposeMap ProGe::NetlistGenerator::glockPorts_
private

Maps global lock ports.

Definition at line 264 of file NetlistGenerator.hh.

Referenced by glockPort(), hasGlockPort(), and mapGlobalLockPort().

◆ glockReqPorts_

PortPurposeMap ProGe::NetlistGenerator::glockReqPorts_
private

Maps global lock request ports.

Definition at line 266 of file NetlistGenerator.hh.

Referenced by glockReqPort(), hasGlockReqPort(), and mapGlobalLockRequestPort().

◆ instructionDecoder_

NetlistBlock* ProGe::NetlistGenerator::instructionDecoder_
private

The instruction decoder block.

Definition at line 276 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and instructionDecoder().

◆ instructionDecompressor_

NetlistBlock* ProGe::NetlistGenerator::instructionDecompressor_
private

The instruction decompressor block.

Definition at line 278 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and instructionDecompressor().

◆ instructionFetch_

NetlistBlock* ProGe::NetlistGenerator::instructionFetch_
private

The instruction fetch block.

Definition at line 280 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and instructionFetch().

◆ iuPortMap_

IUPortMap ProGe::NetlistGenerator::iuPortMap_
private

Maps the created netlist ports to immediate units.

Definition at line 272 of file NetlistGenerator.hh.

Referenced by immediateUnitWritePort(), and mapImmediateUnitWritePort().

◆ loadPortMap_

PortRelationMap ProGe::NetlistGenerator::loadPortMap_
private

Maps loads ports.

Definition at line 254 of file NetlistGenerator.hh.

Referenced by loadPort(), and mapLoadPort().

◆ plugin_

ICDecoderGeneratorPlugin& ProGe::NetlistGenerator::plugin_
private

The generator plugin.

Definition at line 248 of file NetlistGenerator.hh.

Referenced by generate().

◆ portCorrespondenceMap_

PortCorrespondenceMap ProGe::NetlistGenerator::portCorrespondenceMap_
private

Maps the ADF ports to the netlist ports.

Definition at line 250 of file NetlistGenerator.hh.

Referenced by addBaseRFToNetlist(), mapNetlistPort(), netlistPort(), and netlistPortIsMapped().

◆ raInPort_

NetlistPort* ProGe::NetlistGenerator::raInPort_
private

Return address in port in GCU (ifetch).

Definition at line 286 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and gcuReturnAddressInPort().

◆ raOutPort_

NetlistPort* ProGe::NetlistGenerator::raOutPort_
private

Returns address out port in GCU (ifetch).

Definition at line 288 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and gcuReturnAddressOutPort().

◆ rfEntryMap_

RFEntryMap ProGe::NetlistGenerator::rfEntryMap_
private

Maps RF implementations for different RF's.

Definition at line 284 of file NetlistGenerator.hh.

Referenced by addBaseRFToNetlist(), rfEntry(), and ~NetlistGenerator().

◆ rfGuardPorts_

PortPurposeMap ProGe::NetlistGenerator::rfGuardPorts_
private

Maps RF guard ports.

Definition at line 262 of file NetlistGenerator.hh.

Referenced by mapRFGuardPort(), and rfGuardPort().

◆ rfOpcodePortMap_

PortRelationMap ProGe::NetlistGenerator::rfOpcodePortMap_
private

Maps opcode ports.

Definition at line 256 of file NetlistGenerator.hh.

Referenced by hasOpcodePort(), mapRFOpcodePort(), and rfOpcodePort().

◆ rstPorts_

PortPurposeMap ProGe::NetlistGenerator::rstPorts_
private

Maps reset ports.

Definition at line 260 of file NetlistGenerator.hh.

Referenced by mapResetPort(), and rstPort().

◆ unitCorrespondenceMap_

UnitCorrespondenceMap ProGe::NetlistGenerator::unitCorrespondenceMap_
private

Maps the ADF units to the netlist blocks.

Definition at line 252 of file NetlistGenerator.hh.

Referenced by mapNetlistBlock(), and netlistBlock().

The documentation for this class was generated from the following files:
IDF::UnitImplementationLocation
Definition: UnitImplementationLocation.hh:48
LOCK_PORT_NAME
const string LOCK_PORT_NAME
Definition: NetlistGenerator.cc:105
ProGe::NetlistGenerator::isParameterizable
bool isParameterizable(const std::string &paramName, const HDB::FUEntry *fuEntry) const
Definition: NetlistGenerator.cc:1832
HDB::FUArchitecture
Definition: FUArchitecture.hh:55
HDB::FUEntry
Definition: FUEntry.hh:49
HDB::FUExternalPort
Definition: FUExternalPort.hh:52
ProGe::NetlistGenerator::instructionDecompressor_
NetlistBlock * instructionDecompressor_
The instruction decompressor block.
Definition: NetlistGenerator.hh:278
HDB::HWBlockImplementation::clkPort
std::string clkPort() const
Definition: HWBlockImplementation.cc:175
ProGe::NetlistGenerator::DECODER_LOCK_STATUS_PORT
static const std::string DECODER_LOCK_STATUS_PORT
Definition: NetlistGenerator.hh:144
HDB::RFPortImplementation::opcodePortWidthFormula
std::string opcodePortWidthFormula() const
Definition: RFPortImplementation.cc:132
ProGe::NetlistGenerator::addFUToNetlist
void addFUToNetlist(const IDF::FUImplementationLocation &location, NetlistBlock &netlistBlock, std::ostream &warningStream)
Definition: NetlistGenerator.cc:974
TTAMachine::Port::inputSocket
virtual Socket * inputSocket() const
Definition: Port.cc:261
ProGe::SignalType::FETCHBLOCK
@ FETCHBLOCK
Signal is TTA instruction block block containing (compressed) instruction.
ProGe::NetlistGenerator::mapFUOpcodePort
void mapFUOpcodePort(const NetlistBlock &block, NetlistPort &opcodePort)
Definition: NetlistGenerator.cc:1719
ProGe::NetlistGenerator::mapLoadPort
void mapLoadPort(const NetlistPort &port, NetlistPort &loadPort)
Definition: NetlistGenerator.cc:1691
ProGe::NetlistGenerator::loadPortMap_
PortRelationMap loadPortMap_
Maps loads ports.
Definition: NetlistGenerator.hh:254
TCEString::lower
TCEString lower() const
Definition: TCEString.cc:78
HDB::RFEntry::hasImplementation
virtual bool hasImplementation() const
Definition: RFEntry.cc:74
HDB::FUArchitecture::hasParameterizedWidth
bool hasParameterizedWidth(const std::string &port) const
Definition: FUArchitecture.cc:86
TTAMachine::Component::name
virtual TCEString name() const
Definition: MachinePart.cc:125
TTAMachine::Machine::isRISCVMachine
bool isRISCVMachine() const
Definition: Machine.cc:1063
ProGe::NetlistGenerator::rfOpcodePortMap_
PortRelationMap rfOpcodePortMap_
Maps opcode ports.
Definition: NetlistGenerator.hh:256
TTAMachine::FunctionUnit::hasAddressSpace
virtual bool hasAddressSpace() const
Definition: FunctionUnit.cc:608
machine
TTAMachine::Machine * machine
the architecture definition of the estimated processor
Definition: EstimatorCmdLineUI.cc:59
TTAMachine::HWOperation
Definition: HWOperation.hh:52
TTAMachine::AddressSpace
Definition: AddressSpace.hh:51
ProGe::NetlistGenerator::clkPorts_
PortPurposeMap clkPorts_
Maps clock ports.
Definition: NetlistGenerator.hh:258
implementation
IDF::MachineImplementation * implementation
the implementation definition of the estimated processor
Definition: EstimatorCmdLineUI.cc:61
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
ProGe::ProGeContext::adf
const TTAMachine::Machine & adf() const
Definition: ProGeContext.cc:57
ProGe::SignalType::CORE_HALT_STATUS
@ CORE_HALT_STATUS
Signal that tell if core is halted.
ProGe::SignalType::WRITE_BITMASK
@ WRITE_BITMASK
LOCK_STATUS_PORT_NAME
const string LOCK_STATUS_PORT_NAME
Definition: NetlistGenerator.cc:114
RF_NAME_PREFIX
const string RF_NAME_PREFIX
Definition: NetlistGenerator.cc:128
ProGe::NetlistGenerator::addGCUToNetlist
void addGCUToNetlist(NetlistBlock &toplevelBlock, int imemWidthInMAUs)
Definition: NetlistGenerator.cc:692
ProGe::NetlistGenerator::coreBlock_
NetlistBlock * coreBlock_
The TTA core block.
Definition: NetlistGenerator.hh:274
ProGe::NetlistGenerator::DECODER_PC_LOAD_PORT
static const std::string DECODER_PC_LOAD_PORT
PC load port name in instruction decoder.
Definition: NetlistGenerator.hh:136
TTAMachine::FunctionUnit::triggerPort
virtual BaseFUPort * triggerPort() const
Definition: FunctionUnit.cc:267
ProGe::NetlistGenerator::mapGlobalLockRequestPort
void mapGlobalLockRequestPort(const NetlistBlock &block, NetlistPort &glockReqPort)
Definition: NetlistGenerator.cc:1775
HDB::FUPortImplementation
Definition: FUPortImplementation.hh:46
OutOfRange
Definition: Exception.hh:320
ProGe::NetlistGenerator::rfGuardPorts_
PortPurposeMap rfGuardPorts_
Maps RF guard ports.
Definition: NetlistGenerator.hh:262
LOCK_REQUEST_PORT_NAME
const string LOCK_REQUEST_PORT_NAME
Definition: NetlistGenerator.cc:113
HDB::RFEntry
Definition: RFEntry.hh:47
IDF::MachineImplementation::iuImplementation
RFImplementationLocation & iuImplementation(const std::string &iu) const
Definition: MachineImplementation.cc:399
ProGe::SignalType::RESET
@ RESET
Reset signal.
TTAMachine::Port::width
virtual int width() const =0
ProGe::SignalType::WRITE_DATA
@ WRITE_DATA
RA_LOAD_PORT_NAME
const string RA_LOAD_PORT_NAME
Definition: NetlistGenerator.cc:109
ProGe::NetlistPort::direction
Direction direction() const
Definition: NetlistPort.cc:373
ProGe::NetlistGenerator::addBaseRFToNetlist
void addBaseRFToNetlist(const ProGeOptions &options, const TTAMachine::BaseRegisterFile &regFile, const IDF::RFImplementationLocation &location, NetlistBlock &netlistBlock, const std::string &blockNamePrefix)
Definition: NetlistGenerator.cc:1351
HDB::FUArchitecture::architecture
TTAMachine::FunctionUnit & architecture() const
Definition: FUArchitecture.cc:131
MapTools::deleteAllValues
static void deleteAllValues(MapType &aMap)
HDB::RFPortImplementation::direction
Direction direction() const
Definition: RFPortImplementation.cc:88
ProGe::NetlistGenerator::mapResetPort
void mapResetPort(const NetlistBlock &block, NetlistPort &resetPort)
Definition: NetlistGenerator.cc:1747
ProGe::NetlistGenerator::addIUToNetlist
void addIUToNetlist(const ProGeOptions &options, const IDF::RFImplementationLocation &location, NetlistBlock &netlistBlock)
Definition: NetlistGenerator.cc:1318
INSTRUCTIONWIDTH
const string INSTRUCTIONWIDTH
Definition: NetlistGenerator.cc:118
HDB::FUImplementation::externalPort
FUExternalPort & externalPort(int index) const
Definition: FUImplementation.cc:390
READ_ENABLE_PORT_NAME
const string READ_ENABLE_PORT_NAME
Definition: NetlistGenerator.cc:99
ProGe::SignalType::UNDEFINED
@ UNDEFINED
Signal does not have specified usage.
DECOMPRESSOR_BLOCK_NAME
const string DECOMPRESSOR_BLOCK_NAME
Definition: NetlistGenerator.cc:121
ProGe::BIDIR
@ BIDIR
Bidirectional port.
Definition: ProGeTypes.hh:55
DECODER_BLOCK_NAME
const string DECODER_BLOCK_NAME
Definition: NetlistGenerator.cc:122
ProGe::NetlistGenerator::DECODER_PC_OPCODE_PORT
static const std::string DECODER_PC_OPCODE_PORT
PC opcode port name in instruction decoder.
Definition: NetlistGenerator.hh:138
PC_IN_PORT_NAME
const string PC_IN_PORT_NAME
Definition: NetlistGenerator.cc:102
TTAMachine::FunctionUnit::port
virtual BaseFUPort * port(const std::string &name) const
Definition: FunctionUnit.cc:145
TTAMachine::FunctionUnit::addressSpace
virtual AddressSpace * addressSpace() const
Definition: FunctionUnit.cc:580
FETCH_PORT_NAME
const string FETCH_PORT_NAME
Definition: NetlistGenerator.cc:104
ProGe::NetlistGenerator::DECODER_RA_LOAD_PORT
static const std::string DECODER_RA_LOAD_PORT
RA load port name in instruction decoder.
Definition: NetlistGenerator.hh:134
ProGe::NetlistGenerator::glockReqPort
NetlistPort & glockReqPort(const NetlistBlock &block) const
Definition: NetlistGenerator.cc:510
ProGe::NetlistGenerator::findCorrespondingPort
static TTAMachine::FUPort & findCorrespondingPort(const TTAMachine::FunctionUnit &fuToSearch, const TTAMachine::FunctionUnit &origFU, const std::string &portName)
Definition: NetlistGenerator.cc:1963
ProGe::NetlistGenerator::glockPort
NetlistPort & glockPort(const NetlistBlock &block) const
Definition: NetlistGenerator.cc:477
ProGe::NetlistGenerator::isLSU
bool isLSU(const TTAMachine::FunctionUnit &fu) const
Definition: NetlistGenerator.cc:2102
HDB::FUImplementation::opcodePort
std::string opcodePort() const
Definition: FUImplementation.cc:135
RA_IN_PORT_NAME
const string RA_IN_PORT_NAME
Definition: NetlistGenerator.cc:103
TTAMachine::FUPort::isTriggering
virtual bool isTriggering() const
Definition: FUPort.cc:182
ProGe::NetlistGenerator::loadPort
NetlistPort & loadPort(const NetlistPort &port) const
Definition: NetlistGenerator.cc:304
ProGe::NetlistGenerator::glockReqPorts_
PortPurposeMap glockReqPorts_
Maps global lock request ports.
Definition: NetlistGenerator.hh:266
ProGe::NetlistGenerator::netlistBlock
NetlistBlock & netlistBlock(const TTAMachine::Unit &unit) const
Definition: NetlistGenerator.cc:283
Conversion::toString
static std::string toString(const T &source)
HDB::RFArchitecture::width
int width() const
Definition: RFArchitecture.cc:343
PC_OPCODE_PORT_NAME
const string PC_OPCODE_PORT_NAME
Definition: NetlistGenerator.cc:110
ProGe::NetlistGenerator::FETCHBLOCK_PORT_NAME
static const std::string FETCHBLOCK_PORT_NAME
Definition: NetlistGenerator.hh:154
ProGe::NetlistBlock::addPackage
void addPackage(const std::string &packageName)
Definition: BaseNetlistBlock.cc:687
ProGe::NetlistGenerator::isLSUDataPort
static bool isLSUDataPort(const TTAMachine::FunctionUnit &adfFU, const std::string &portName)
Definition: NetlistGenerator.cc:2132
TTAMachine::RFPort
Definition: RFPort.hh:45
TTAMachine::BaseRegisterFile::numberOfRegisters
virtual int numberOfRegisters() const
HDB::RFEntry::architecture
RFArchitecture & architecture() const
Definition: RFEntry.cc:145
ProGe::SignalGroupType::INSTRUCTION_LINE
@ INSTRUCTION_LINE
Signal group type for serial TTA instruction bus.
ProGe::NetlistGenerator::opcodePortWidth
static int opcodePortWidth(const HDB::FUEntry &fu, std::ostream &warningStream)
Definition: NetlistGenerator.cc:1889
ProGe::SignalType::WRITEMODE
@ WRITEMODE
Signal to choose mode for READ_WRITE_REQUEST or similar.
HDB::HWBlockImplementation::rstPort
std::string rstPort() const
Definition: HWBlockImplementation.cc:197
ProGe::NetlistGenerator::DECODER_LOCK_REQ_IN_PORT
static const std::string DECODER_LOCK_REQ_IN_PORT
Lock request in port name in instruction decoder.
Definition: NetlistGenerator.hh:142
HDB::FUImplementation::glockReqPort
std::string glockReqPort() const
Definition: FUImplementation.cc:157
IDF::MachineImplementation::rfImplementation
RFImplementationLocation & rfImplementation(const std::string &rf) const
Definition: MachineImplementation.cc:377
assert
#define assert(condition)
Definition: Application.hh:86
ProGe::NetlistGenerator::addRFToNetlist
void addRFToNetlist(const ProGeOptions &options, const IDF::RFImplementationLocation &location, NetlistBlock &netlistBlock)
Definition: NetlistGenerator.cc:1289
TTAMachine::FunctionUnit
Definition: FunctionUnit.hh:55
ProGe::ActiveState::LOW
@ LOW
HDB::FUImplementation::parameterCount
int parameterCount() const
Definition: FUImplementation.cc:443
ProGe::NetlistGenerator::addGeneratableFUsToNetlist
GeneratableFUNetlistBlock * addGeneratableFUsToNetlist(const IDF::FUGenerated &fug, NetlistBlock &netlistBlock)
Definition: NetlistGenerator.cc:898
TTAMachine::HWOperation::port
virtual FUPort * port(int operand) const
Definition: HWOperation.cc:320
ProGe::NetlistGenerator::context_
const ProGeContext & context_
Definition: NetlistGenerator.hh:246
IMEMWIDTHFORMULA
const string IMEMWIDTHFORMULA
Definition: NetlistGenerator.cc:117
TTAMachine::FUPort
Definition: FUPort.hh:46
ProGe::NetlistGenerator::clkPort
NetlistPort & clkPort(const NetlistBlock &block) const
Definition: NetlistGenerator.cc:425
ProGe::NetlistGenerator::DECODER_CLOCK_PORT
static const std::string DECODER_CLOCK_PORT
Clock port name in instruction decoder.
Definition: NetlistGenerator.hh:132
HDB::RFExternalPort
Definition: RFExternalPort.hh:41
HDB::RFImplementation
Definition: RFImplementation.hh:50
TTAMachine::Machine::controlUnit
virtual ControlUnit * controlUnit() const
Definition: Machine.cc:345
TTAMachine::HWOperation::io
int io(const FUPort &port) const
Definition: HWOperation.cc:364
BUSY_PORT_NAME
const string BUSY_PORT_NAME
Definition: NetlistGenerator.cc:98
ProGe::NetlistGenerator::mapRFGuardPort
void mapRFGuardPort(const NetlistBlock &block, NetlistPort &guardPort)
Definition: NetlistGenerator.cc:1789
HDB::FUEntry::hasArchitecture
virtual bool hasArchitecture() const
Definition: FUEntry.cc:117
TTAMachine::HWOperation::name
const std::string & name() const
Definition: HWOperation.cc:141
InvalidData
Definition: Exception.hh:149
ProGe::NetlistGenerator::fuOpcodePorts_
PortPurposeMap fuOpcodePorts_
Maps FU opcode ports.
Definition: NetlistGenerator.hh:270
ProGe::NetlistGenerator::mapNetlistBlock
void mapNetlistBlock(const TTAMachine::Unit &unit, NetlistBlock &netlistBlock)
Definition: NetlistGenerator.cc:1668
ProGe::NetlistGenerator::context
const ProGeContext & context() const
Definition: NetlistGenerator.hh:125
TTAMachine::Machine::immediateUnitNavigator
virtual ImmediateUnitNavigator immediateUnitNavigator() const
Definition: Machine.cc:416
TTAMachine::ControlUnit
Definition: ControlUnit.hh:50
THROW_EXCEPTION
#define THROW_EXCEPTION(exceptionType, message)
Exception wrapper macro that automatically includes file name, line number and function name where th...
Definition: Exception.hh:39
ProGe::NetlistGenerator::glockPorts_
PortPurposeMap glockPorts_
Maps global lock ports.
Definition: NetlistGenerator.hh:264
TTAMachine::Port
Definition: Port.hh:54
HDB::ExternalPort::parameterDependency
std::string parameterDependency(int index) const
Definition: ExternalPort.cc:203
ProGe::NetlistGenerator::rstPorts_
PortPurposeMap rstPorts_
Maps reset ports.
Definition: NetlistGenerator.hh:260
HDB::Direction
Direction
Direction of port.
Definition: HDBTypes.hh:40
HDB::BIDIR
@ BIDIR
Bidirectional port.
Definition: HDBTypes.hh:43
TTAMachine::Machine::Navigator::hasItem
bool hasItem(const std::string &name) const
HDB::FUEntry::architecture
FUArchitecture & architecture() const
Definition: FUEntry.cc:129
HDB::FUArchitecture::portDirection
HDB::Direction portDirection(const std::string &port) const
Definition: FUArchitecture.cc:145
ProGe::NetlistGenerator::unitCorrespondenceMap_
UnitCorrespondenceMap unitCorrespondenceMap_
Maps the ADF units to the netlist blocks.
Definition: NetlistGenerator.hh:252
ProGe::NetlistGenerator::raOutPort_
NetlistPort * raOutPort_
Returns address out port in GCU (ifetch).
Definition: NetlistGenerator.hh:288
ProGe::NetlistGenerator::plugin_
ICDecoderGeneratorPlugin & plugin_
The generator plugin.
Definition: NetlistGenerator.hh:248
TTAMachine::HWOperation::isBound
bool isBound(const FUPort &port) const
Definition: HWOperation.cc:338
__func__
#define __func__
Definition: Application.hh:67
ProGe::NetlistGenerator::DECODER_INSTR_WORD_PORT
static const std::string DECODER_INSTR_WORD_PORT
Instruction word port name in instruction decoder.
Definition: NetlistGenerator.hh:128
TTAMachine::Machine::functionUnitNavigator
virtual FunctionUnitNavigator functionUnitNavigator() const
Definition: Machine.cc:380
ProGe::NetlistGenerator::netlistPortIsMapped
bool netlistPortIsMapped(const TTAMachine::Port &adfPort)
Definition: NetlistGenerator.cc:1681
INSTANCE_SUFFIX
const TCEString INSTANCE_SUFFIX
Definition: NetlistGenerator.cc:131
ProGe::NetlistGenerator::DECODER_RESET_PORT
static const std::string DECODER_RESET_PORT
Reset port name in instruction decoder.
Definition: NetlistGenerator.hh:130
HDB::Parameter::type
std::string type
Type of the parameter.
Definition: HDBTypes.hh:48
ProGe::Netlist::connectClocks
static void connectClocks(NetlistBlock &block)
Definition: Netlist.cc:483
ADDRESS_PORT_NAME
const string ADDRESS_PORT_NAME
Definition: NetlistGenerator.cc:100
TTAMachine::FunctionUnit::operationCount
virtual int operationCount() const
Definition: FunctionUnit.cc:419
HDB::HDBManager
Definition: HDBManager.hh:82
TTAMachine::BaseFUPort::setWidth
void setWidth(int width)
Definition: BaseFUPort.cc:121
ProGe::NetlistGenerator::fuEntryMap_
FUEntryMap fuEntryMap_
Maps FU implementations for different FU's.
Definition: NetlistGenerator.hh:282
ProGe::NetlistGenerator::mapRFOpcodePort
void mapRFOpcodePort(const NetlistPort &port, NetlistPort &opcodePort)
Definition: NetlistGenerator.cc:1705
RESET_PORT_NAME
const string RESET_PORT_NAME
Definition: NetlistGenerator.cc:96
ProGe::ProGeContext::idf
const IDF::MachineImplementation & idf() const
Definition: ProGeContext.cc:62
MathTools::requiredBits
static int requiredBits(unsigned long int number)
ProGe::NetlistGenerator::inferLSUSignal
static Signal inferLSUSignal(const std::string &portName)
Definition: NetlistGenerator.cc:2151
HDB::RFEntry::implementation
RFImplementation & implementation() const
Definition: RFEntry.cc:102
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
TTAMachine::FunctionUnit::hasOperation
virtual bool hasOperation(const std::string &name) const
Definition: FunctionUnit.cc:330
ProGe::SignalType::ADDRESS
@ ADDRESS
Signal holds address.
HDB::PortImplementation::loadPort
std::string loadPort() const
Definition: PortImplementation.cc:96
ProGe::Netlist::connectResets
static void connectResets(NetlistBlock &block)
Definition: Netlist.cc:511
ProGe::SignalType::CLOCK
@ CLOCK
Clock signal.
Exception
Definition: Exception.hh:54
ProGe::SignalGroupType::BITMASKED_SRAM_PORT
@ BITMASKED_SRAM_PORT
Signal group type for one port SRAM having read and write capability and bitmask for writing.
ProGe::ProGeContext::coreEntityName
const std::string & coreEntityName() const
Definition: ProGeContext.cc:77
ProGe::SignalType::READ_WRITE_REQUEST
@ READ_WRITE_REQUEST
Signal to make either read or write request.
ProGe::NetlistGenerator::rstPort
NetlistPort & rstPort(const NetlistBlock &block) const
Definition: NetlistGenerator.cc:446
IDF::UnitImplementationLocation::unitName
virtual std::string unitName() const
Definition: UnitImplementationLocation.cc:138
IU_NAME_PREFIX
const string IU_NAME_PREFIX
Definition: NetlistGenerator.cc:129
TTAMachine::FunctionUnit::operationPortCount
virtual int operationPortCount() const
Definition: FunctionUnit.cc:182
TTAMachine::Port::isOutput
virtual bool isOutput() const
Definition: Port.cc:308
TTAMachine::Unit::portCount
virtual int portCount() const
Definition: Unit.cc:135
ProGe::NetlistGenerator::instructionDecoder_
NetlistBlock * instructionDecoder_
The instruction decoder block.
Definition: NetlistGenerator.hh:276
Exception::errorMessage
std::string errorMessage() const
Definition: Exception.cc:123
ProGe::SignalType::READ_REQUEST_READY
@ READ_REQUEST_READY
Signal to tell that requested data can be read.
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
options
static MachInfoCmdLineOptions options
Definition: MachInfo.cc:46
TTAMachine::FunctionUnit::hasOperationPort
virtual bool hasOperationPort(const std::string &name) const
Definition: FunctionUnit.cc:204
ProGe::NetlistGenerator::instructionMemory
static TTAMachine::AddressSpace & instructionMemory(const TTAMachine::Machine &machine)
Definition: NetlistGenerator.cc:2041
ProGe::NetlistGenerator::raInPort_
NetlistPort * raInPort_
Return address in port in GCU (ifetch).
Definition: NetlistGenerator.hh:286
HDB::RFArchitecture::hasGuardSupport
bool hasGuardSupport() const
Definition: RFArchitecture.cc:519
TTAMachine::AddressSpace::width
virtual int width() const
Definition: AddressSpace.cc:155
HDB::Parameter::name
std::string name
Name of the parameter.
Definition: HDBTypes.hh:47
ProGe::SignalType::READ_REQUEST
@ READ_REQUEST
Signal to make read request.
HDB::FUImplementation
Definition: FUImplementation.hh:53
PC_LOAD_PORT_NAME
const string PC_LOAD_PORT_NAME
Definition: NetlistGenerator.cc:108
HDB::RFArchitecture
Definition: RFArchitecture.hh:50
ProGe::SignalType::READ_DATA
@ READ_DATA
HDB::RFPortImplementation
Definition: RFPortImplementation.hh:43
TTAMachine::BaseRegisterFile::port
virtual RFPort * port(const std::string &name) const
Definition: BaseRegisterFile.cc:129
TTAMachine::Machine::registerFileNavigator
virtual RegisterFileNavigator registerFileNavigator() const
Definition: Machine.cc:450
ProGe::NetlistGenerator::rfEntryMap_
RFEntryMap rfEntryMap_
Maps RF implementations for different RF's.
Definition: NetlistGenerator.hh:284
MapTools::containsKey
static bool containsKey(const MapType &aMap, const KeyType &aKey)
HDB::FUPortImplementation::architecturePort
std::string architecturePort() const
Definition: FUPortImplementation.cc:93
IllegalMachine
Definition: Exception.hh:878
HDB::PortImplementation::name
std::string name() const
Definition: PortImplementation.cc:74
ProGe::NetlistBlock::addSubBlock
void addSubBlock(BaseNetlistBlock *subBlock, const std::string &instanceName="")
Definition: BaseNetlistBlock.cc:405
ProGe::NetlistGenerator::portCorrespondenceMap_
PortCorrespondenceMap portCorrespondenceMap_
Maps the ADF ports to the netlist ports.
Definition: NetlistGenerator.hh:250
IDF::UnitImplementationLocation::id
virtual int id() const
Definition: UnitImplementationLocation.cc:127
TTAMachine::FunctionUnit::hasOperationLowercase
virtual bool hasOperationLowercase(const std::string &name) const
Definition: FunctionUnit.cc:341
ProGe::NetlistGenerator::iuPortMap_
IUPortMap iuPortMap_
Maps the created netlist ports to immediate units.
Definition: NetlistGenerator.hh:272
TTAMachine::Port::name
virtual std::string name() const
Definition: Port.cc:141
IMEMADDRWIDTH
const string IMEMADDRWIDTH
Definition: NetlistGenerator.cc:116
ProGe::NetlistGenerator::calculateAddressWidth
unsigned int calculateAddressWidth(TTAMachine::FunctionUnit const *fu) const
Definition: NetlistGenerator.cc:1856
HDB::FUImplementation::parameter
Parameter parameter(int index) const
Definition: FUImplementation.cc:457
TCEString
Definition: TCEString.hh:53
HDB::RFPortImplementation::opcodePort
std::string opcodePort() const
Definition: RFPortImplementation.cc:110
HDB::FUImplementation::architecturePortCount
int architecturePortCount() const
Definition: FUImplementation.cc:326
ProGe::NetlistGenerator::mapClockPort
void mapClockPort(const NetlistBlock &block, NetlistPort &clkPort)
Definition: NetlistGenerator.cc:1733
ProGe::NetlistGenerator::checkInstanceName
TCEString checkInstanceName(const TCEString &baseInstanceName, const TCEString &moduleName) const
Definition: NetlistGenerator.cc:2080
ProGe::NetlistGenerator::mapGlobalLockPort
void mapGlobalLockPort(const NetlistBlock &block, NetlistPort &glockPort)
Definition: NetlistGenerator.cc:1761
HDB::IN
@ IN
Input port.
Definition: HDBTypes.hh:41
TTAMachine::Port::outputSocket
virtual Socket * outputSocket() const
Definition: Port.cc:281
ProGe::NetlistGenerator::DECODER_LOCK_REQ_OUT_PORT
static const std::string DECODER_LOCK_REQ_OUT_PORT
Lock request out port name in instruction decoder.
Definition: NetlistGenerator.hh:140
ProGe::NetlistBlock::addPortGroup
void addPortGroup(NetlistPortGroup *portGroup)
Definition: BaseNetlistBlock.cc:508
TTAMachine::Port::isInput
virtual bool isInput() const
Definition: Port.cc:298
HDB::RFArchitecture::size
int size() const
Definition: RFArchitecture.cc:326
HDB::Parameter::value
std::string value
Value of the parameter.
Definition: HDBTypes.hh:49
ProGe::NetlistGenerator::netlistPort
NetlistPort & netlistPort(const TTAMachine::Port &port, Direction dir=IN) const
Definition: NetlistGenerator.cc:247
RA_OUT_PORT_NAME
const string RA_OUT_PORT_NAME
Definition: NetlistGenerator.cc:97
GLOBAL_LOCK_PORT_NAME
const string GLOBAL_LOCK_PORT_NAME
Definition: NetlistGenerator.cc:112
ProGe::ICDecoderGeneratorPlugin::completeNetlist
virtual void completeNetlist(NetlistBlock &netlistBlock, const NetlistGenerator &generator)=0
TTAMachine::Machine::Navigator::item
ComponentType * item(int index) const
HDB::Parameter
Definition: HDBTypes.hh:46
KeyNotFound
Definition: Exception.hh:285
HDB::HWBlockImplementation::moduleName
std::string moduleName() const
Definition: HWBlockImplementation.cc:153
TTAMachine::FunctionUnit::operation
virtual HWOperation * operation(const std::string &name) const
Definition: FunctionUnit.cc:363
INSTRUCTIONWORD_PORT_NAME
const string INSTRUCTIONWORD_PORT_NAME
Definition: NetlistGenerator.cc:111
IDF::UnitImplementationLocation::hdbFile
virtual std::string hdbFile() const
Definition: UnitImplementationLocation.cc:99
TTAMachine::RegisterFile
Definition: RegisterFile.hh:47
HDB::ExternalPort::name
std::string name() const
Definition: ExternalPort.cc:84
ProGe::NetlistGenerator::addFUExternalPortsToNetlist
void addFUExternalPortsToNetlist(const HDB::FUImplementation &fuImplementation, NetlistBlock &coreBlock, NetlistBlock &fuBlock, const TTAMachine::FunctionUnit &adfFU)
Definition: NetlistGenerator.cc:1189
ProGe::NetlistGenerator::instructionFetch_
NetlistBlock * instructionFetch_
The instruction fetch block.
Definition: NetlistGenerator.hh:280
TTAMachine::FunctionUnit::operationPort
virtual FUPort * operationPort(const std::string &name) const
Definition: FunctionUnit.cc:224
ProGe::NetlistGenerator::fuEntry
HDB::FUEntry & fuEntry(const std::string &fuName) const
Definition: NetlistGenerator.cc:657
HDB::FUEntry::hasImplementation
virtual bool hasImplementation() const
Definition: FUEntry.cc:74
IDF::MachineImplementation::fuImplementation
FUImplementationLocation & fuImplementation(const std::string &fu) const
Definition: MachineImplementation.cc:355
HDB::FUEntry::implementation
FUImplementation & implementation() const
Definition: FUEntry.cc:86
HDB::HWBlockImplementation::glockPort
std::string glockPort() const
Definition: HWBlockImplementation.cc:219
FU_NAME_PREFIX
const string FU_NAME_PREFIX
Definition: NetlistGenerator.cc:127
TTAMachine::ControlUnit::returnAddressPort
SpecialRegisterPort * returnAddressPort() const
Definition: ControlUnit.cc:307
IDF::FUGenerated::name
std::string name() const
Definition: FUGenerated.cc:103
ProGe::NetlistGenerator::fuGuardPortMap_
PortRelationMap fuGuardPortMap_
Maps FU guard ports.
Definition: NetlistGenerator.hh:268
HDB::FUPortImplementation::guardPort
std::string guardPort() const
Definition: FUPortImplementation.cc:115
ProGe::NetlistGenerator::mapImmediateUnitWritePort
void mapImmediateUnitWritePort(const TTAMachine::ImmediateUnit &iu, NetlistPort &port)
Definition: NetlistGenerator.cc:1818
TTAMachine::BaseRegisterFile::width
virtual int width() const
IDF::MachineImplementation::FUGenerations
const std::vector< FUGenerated > & FUGenerations() const
Definition: MachineImplementation.cc:1572
HDB::HDBManager::fuByEntryID
FUEntry * fuByEntryID(RowID id) const
Definition: HDBManager.cc:2828
HDB::ExternalPort::direction
Direction direction() const
Definition: ExternalPort.cc:106
TTAMachine::AddressSpace::start
virtual ULongWord start() const
Definition: AddressSpace.cc:166
TTAMachine::AddressSpace::end
virtual ULongWord end() const
Definition: AddressSpace.cc:177
ProGe::NetlistGenerator::mapFUGuardPort
void mapFUGuardPort(const NetlistPort &dataPort, NetlistPort &guardPort)
Definition: NetlistGenerator.cc:1803
HDB::FUImplementation::architecturePort
FUPortImplementation & architecturePort(int index) const
Definition: FUImplementation.cc:351
HDB::ExternalPort::widthFormula
std::string widthFormula() const
Definition: ExternalPort.cc:128
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53
HDB::OUT
@ OUT
Output port.
Definition: HDBTypes.hh:42
CLOCK_PORT_NAME
const string CLOCK_PORT_NAME
Definition: NetlistGenerator.cc:95
HDB::RFEntry::hasArchitecture
virtual bool hasArchitecture() const
Definition: RFEntry.cc:117
ProGe::NetlistGenerator::translateDirection
static Direction translateDirection(HDB::Direction direction)
Definition: NetlistGenerator.cc:2059
HDB::FUImplementation::externalPortCount
int externalPortCount() const
Definition: FUImplementation.cc:337
IFETCH_BLOCK_NAME
const string IFETCH_BLOCK_NAME
Definition: NetlistGenerator.cc:120
HDB::ExternalPort::parameterDependencyCount
int parameterDependencyCount() const
Definition: ExternalPort.cc:189
TTAMachine::BaseFUPort::width
virtual int width() const
Definition: BaseFUPort.cc:109
ProGe::NetlistGenerator::GeneratableFUNetlistBlock
friend class GeneratableFUNetlistBlock
Definition: NetlistGenerator.hh:85
InstanceNotFound
Definition: Exception.hh:304
HDB::HDBManager::rfByEntryID
RFEntry * rfByEntryID(RowID id) const
Definition: HDBManager.cc:2885
HDB::FUPortImplementation::widthFormula
std::string widthFormula() const
Definition: FUPortImplementation.cc:137
DATA_PORT_NAME
const string DATA_PORT_NAME
Definition: NetlistGenerator.cc:101
TTAMachine::Port::parentUnit
Unit * parentUnit() const
ProGe::NetlistGenerator::mapNetlistPort
void mapNetlistPort(const TTAMachine::Port &adfPort, NetlistPort &netlistPort)
Definition: NetlistGenerator.cc:1650
TTAMachine::ImmediateUnit
Definition: ImmediateUnit.hh:50
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