Todo List

Member BaseLineReader::readLine (std::string prompt="")

Implement detection of end-of-file.

Member BasicBlockPass::handleBasicBlock (TTAProgram::BasicBlock &basicBlock, const TTAMachine::Machine &targetMachine, TTAProgram::InstructionReferenceManager &irm, BasicBlockNode *bbn=NULL)

: Why both BB and BBN as arguments? If BBN is needed then I think BB argument can be replaced with a BBN one. We always should have it anyways.

Member BasicBlockScheduler::handleRemovedResultMoves (std::set< std::pair< TTAProgram::Move *, int > > removedMoves)

: reschedule also the moves dependent from the rescheduled ones that got earlier

Member BBSchedulerController::handleProcedure (TTAProgram::Procedure &procedure, const TTAMachine::Machine &targetMachine) override

remove the targetMachine argument. The machine is given in the constructor and assumed to be the same for whole lifetime of the scheduler instance.

Namespace boost::assign

These two lines can be removed after C++11 features can be used in the source code, since it has native support for initializing std::map.

Member BOOST_NO_HASH

Check for STLport hash_map

Check for Intel's compiler. It seems Intel's compiler provides compatibility for GNU so HASHMAP_GNU_EXT gets defined.

Member BoostGraph< GraphNode, GraphEdge >::Node

What's the point of these typedefs?

Member CmdLineOptions::optionGiven (std::string key) const

: This returns always true if trying to find added CmdLineOption...

Member CommandsCommand::execute (const std::vector< DataObject > &arguments)

Use the count for the step.

Member CommandsCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member CompiledSimCodeGenerator::handleOperation (const TTAMachine::HWOperation &op)

maybe use IsCall & IsControlFlowOperation.

Member CompiledSimCodeGenerator::handleOperationWithoutDag (const TTAMachine::HWOperation &op)

maybe use IsCall & IsControlFlowOperation.

Member ConditionCommand::execute (const std::vector< DataObject > &arguments)

Use the count for the step.

Member ConditionCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member ConfCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member ControlDependenceEdge::invertEdgePredicate ()

this should be handled better, after the ownership of CDG is moved into the PDG or so

Member ControlFlowGraph::~ControlFlowGraph ()

: this routine is O(n�)

Member DataDependenceEdge::toString (MoveNode &tail) const

This should be refactored.

Member DataDependenceGraph::addNode (MoveNode &moveNode, MoveNode &relatedNode)

: also add to subgrapsh which have the related node?

Member DataDependenceGraph::copyDependencies (const MoveNode &src, MoveNode &dst, bool ignoreSameBBBackedges, bool moveOverLoopEdge=true)

should this method be in base class? would require graphedge.clone()

Member DataDependenceGraph::earliestCycle (const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegWaRs=false, bool ignoreRegWaWs=false, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false, bool assumeBypassing=false) const

clean this up: should be the same code as the edgeWeight when EWH_REAL is used.

Member DataDependenceGraph::edgeWeight (DataDependenceEdge &e, const MoveNode &hNode) const

EWH_HEURISTIC is incomplete. It should take in account the number of resources in the current target machine and not assume a "generic machine".

Member DataDependenceGraph::latestCycle (const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegAntideps=false, bool ignoreUnscheduledSuccessors=true, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false) const

Consider the latency for result read move!

Member DefaultICDecoderEstimator::estimateICArea (HDB::HDBRegistry &hdbRegistry, const TTAMachine::Machine &machine, const IDF::MachineImplementation &machineImplementation, AreaInGates &area)

each socket may have own HDB associated to their implementation location object

each bus may have own HDB associated to their implementation location object

Member DeleteBPCommand::execute (const std::vector< DataObject > &arguments)

Use the count for the step.

Member DeleteBPCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member DisableBPCommand::execute (const std::vector< DataObject > &arguments)

Use the count for the step.

Member DisableBPCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member DisassembleCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member EnableBPCommand::execute (const std::vector< DataObject > &arguments)

Use the count for the step.

Member EnableBPCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member ExplorerCmdLineOptions::ExplorerCmdLineOptions ()

Use textgenerator in the help texts.

Member ExplorerCmdLineOptions::printHelp () const

Implement using ExplorerTextGenerator.

Member FrequencySweepExplorer::explore (const RowID &startPointConfigurationID, const unsigned int &)

Optimization of the instruction size not required for 1st version!

Final optimization/tuning not required for 1st version!

Member FUState::advanceClock ()

detect if there are clocked state objects

detect if there are clocked state objects

Member HDB::HDBManager::costEstimationDataValue (const std::string &valueName, const std::string &pluginName) const

Another version for fetching lists of data.

Member HDB::HDBManager::fuCostEstimationData (const std::string &valueName, RowID implementationId, const std::string &pluginName) const

Another version for fetching lists of data.

Refactor most of the code in *costEstimationData() functions to a helper function

Member HDB::HDBManager::rfCostEstimationData (const std::string &valueName, RowID implementationId, const std::string &pluginName) const

Another version for fetching lists of data.

Member HelpCommand::helpText () const

TextGenerator.

Member IgnoreCommand::execute (const std::vector< DataObject > &arguments)

Use the count for the step.

Member IgnoreCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member InputPSocketBroker::assign (int cycle, MoveNode &node, SchedulingResource &res, int immWriteCycle, int immRegIndex) override

Add caching of assigned resource objects (a MoveNode-Resource mapping).

Member InputPSocketBroker::unassign (MoveNode &node) override

Remove from cache of assigned resource objects.

Member ITemplateBroker::isApplicable (const MoveNode &node, const TTAMachine::Bus *) const override

reconsider, should be applicable for all the MoveNodes

Member KillCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Namespace llvm

a Proper targetLowering for more accurate targetTransformInfo

Member llvm::TCETargetLowering::LowerFormalArguments (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLOC_PARAM_TYPE dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override

This probably doesn't work with vector arguments currently.

Member MachCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member MachineStateBuilder::addVirtualOpcodeSettingPortsToFU (MachineState &machineState, FUState &state, TTAMachine::FunctionUnit &unit)

Improve this and change the naming to alu.add.p1, or save the virtual ports to different index!

Member MachineStateBuilder::buildMachineState (const TTAMachine::Machine &machine, MemorySystem &memSys, StateLocator &locator)

This assumes that natural word width of GCU is 4 MAUs!

Member main (int argc, char *argv[])

: read command line options and initialize the simulator (frontend) using the given values.

Member MemoryAccessingFUState::MemoryAccessingFUState (Memory &memory)

Do not hard code the MAU or NW sizes!

Member MemoryAccessingFUState::MemoryAccessingFUState (const TCEString &name, Memory &memory)

Do not hard code the MAU or NW sizes!

Member MemorySystem::memoryConst (const TTAMachine::AddressSpace &as) const

These methods need to be changed to compare with the AS attributes not with AS pointer!

Member MoveNodeGroup::earliestCycle (bool assumeBypassing=false) const

What is the "leader node", in general, in an unassigned operation?

Member MultiLatencyOperationExecutor::startOperation (Operation &op)

This can be optimized a lot: try to initialize the vector as rarely as possible.

Member OperationDAGSelector::createExpandedDAG (const Operation &op, OperationSet &opSet)

Implement function when neccessary. Right now returns DAG for operation that has smallest number of operations that are not found in given opset.

Class ProGe::ICDecoderGeneratorPlugin

Add rest of the methods.

Member QuitCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

File RegisterCopyAdder.cc

rename the file to match the class name

Member RegisterCopyAdder::addConnectionRegisterCopiesImmediate (MoveNode &originalMove, const TTAMachine::Port &destinationPort, bool countOnly=true, DataDependenceGraph *ddg=NULL, DataDependenceGraph::NodeSet *addedNodes=NULL)

check that the buses support the guard of the original move

Member RegisterCopyAdder::fixDDGEdgesInTempReg (DataDependenceGraph &ddg, MoveNode &originalMove, MoveNode *firstMove, MoveNode *lastMove, const TTAMachine::RegisterFile *lastRF, int lastRegisterIndex, BasicBlockNode &currentBBNode, bool bottomUpScheduling, bool loopScheduling)

currently leaves some inter-bb-antidependencies out, these are caught later when doing delay slot filling in order to get it working.

Member RegisterCopyAdder::fixDDGEdgesInTempRegChain (DataDependenceGraph &ddg, MoveNode &originalMove, MoveNode *firstMove, std::vector< MoveNode * > intMoves, MoveNode *lastMove, const TTAMachine::RegisterFile *firstRF, std::vector< const TTAMachine::RegisterFile * > intRF, const TTAMachine::RegisterFile *lastRF, int firstRegisterIndex, std::vector< int > intRegisterIndex, int lastRegisterIndex, int regsRequired, BasicBlockNode &currentBBNode)

currently leaves some inter-bb-antidependencies out, these are caught later when doing delay slot filling in order to get it working.

Member RegisterCopyAdder::fixDDGEdgesInTempRegChainImmediate (DataDependenceGraph &ddg, MoveNode &originalMove, MoveNode *firstMove, MoveNode *regToRegCopy, MoveNode *lastMove, const TTAMachine::RegisterFile *tempRF1, const TTAMachine::RegisterFile *tempRF2, int tempRegisterIndex1, int tempRegisterIndex2, BasicBlockNode &currentBBNode)

currently leaves some inter-bb-antidependencies out, these are caught later when doing delay slot filling in order to get it working.

File RegisterRenamer.cc

rename the file to match the class name

Member RegisterState::value_

Fix this mutable mess. It's needed because OutputPortState needs to mask the value_ in its value() implementation.

File RelationalDBQueryResult.cc

Change returning UNKNOWN_INDEX to throwing an exception.

Member ResourceConstraintAnalyzer::optimalScheduleResourceUsage (DataDependenceGraph &ddg, TCEString graphName)

this is incomplete as the operand to trigger edges are missing, thus the analysis results are likely to be false.

Member ResumeCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member RFPortCheck::check (const TTAMachine::Machine &mach, MachineCheckResults &results) const

Check if there is no read ports and the register file has at least one register which is not a predicate reg (read by GCU).

Member RunCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member SettingCommand::execute (const std::vector< DataObject > &arguments)

Use the count for the step.

Member SettingCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member SimControlLanguageCommand::parseBreakpoint (const std::vector< DataObject > &arguments, Breakpoint &target)

set the condition, if any

Member SimControlLanguageCommand::printStopReasons ()

the stop reason code to string conversion should be externalized to another function.

Member SimpleOperationExecutor::startOperation (Operation &op)

This can be optimized a lot: try to initialize the vector as rarely as possible.

create valueConst() and value() to avoid these uglies

Fix! This should not probably be assumed, or at least user should be notified if his operand ids are not what are expected.

Member SimulatorCmdLineOptions::printHelp () const

Implement using SimulatorTextGenerator.

Member SimulatorCmdLineOptions::SimulatorCmdLineOptions ()

Use textgenerator in the help texts.

Member SimulatorFrontend::currentProcedure () const

Throw exception if simulation is not initialized

Member SimulatorFrontend::cycleCount () const

Throw exception if simulation is not initialized

Member SimulatorFrontend::disassembleInstruction (UIntWord instructionAddress) const

print all labels associated at address

Member SimulatorFrontend::eventHandler ()

This should probably be an inline function as it used to be in the SimulatorToolbox class...

Member SimulatorFrontend::findBooleanRegister ()

Improve evaluation when the correct way is known.

Member SimulatorFrontend::findPort (const std::string &fuName, const std::string &portName)

Get the list of control operations from GCU instead of hard coding like this

Member SimulatorFrontend::findRegister (const std::string &rfName, int registerIndex)

Improve evaluation when the parallel assembler syntax is known.

Member SimulatorFrontend::loadProgram (const std::string &fileName)

Implement after Program builder is done.

Throw when machine is not loaded.

Implement checking for already running simulation.

Member SimulatorFrontend::loadProgram (const TTAProgram::Program &program)

Throw when machine is not loaded.

Implement checking for already running simulation.

Member SimulatorFrontend::memorySystem (int coreId=-1)

Throw instead.

Member SimulatorFrontend::next (int count=1)

Throw exception if simulation is not initialized.

Member SimulatorFrontend::programCounter () const

Throw exception if simulation is not initialized

Member SimulatorFrontend::run ()

Throw exception if simulation is not initialized.

Member SimulatorFrontend::runUntil (UIntWord address)

Throw exception if simulation is not initialized.

Member SimulatorFrontend::state (std::string searchString)

Parallel fu port access (syntax?)

Member SimulatorFrontend::step (double count=1)

Throw exception if simulation is not initialized.

Member SimulatorFrontend::utilizationStatistics (int core=-1)

: unimplemented for remote debuggers

Member SimValue::operator== (const SimValue &rightHand) const

Should this be changed to comparison between bytes from the whole bitwidth?

Member SimValue::swapByteOrder (const Byte *from, size_t byteCount, Byte *to) const

This currently works, but there could be more optimal 8-byte, 4-byte and 2-byte swapper functions for 2/4/8 byte swaps. The more optimal swappers would load all bytes to 8, 4 or 2-byte values and shift invidivual bytes to their correct places, which would reduce memory accesses. Or use some intrincs for optimal execution and better code density.

Member StepiCommand::execute (const std::vector< DataObject > &arguments)

Use the count for the step.

Member StepiCommand::helpText () const

Use SimulatorTextGenerator to get the help text.

Member StopPointManager::findStopPoint (unsigned int handle)

textgenerator, to be displayed in the UI.

Member StopPointManager::stopPointHandle (unsigned int index)

textgenerator, to be displayed in the UI.

Member StopPointManager::stopPointWithHandleConst (unsigned int handle) const

textgenerator, to be displayed in the UI.

Member TclInterpreter::interpret (const std::string &commandLine)

This does not work with nested loops correctly! It stops after it encouters the first line with only "}", thus it stops after the nested loop definition stops.

Member TDGen::analyzeMachineRegisters ()

Apparently TDGen does not write information of 8 bit registers -> can't add them.

Member TDGen::operandToString (const Operand &operand, bool match, char operandType, const std::string &immDefName="")

Vector of pointers once supported. Change operand types for GATHER and SCATTER to be mem-data and mem-address, because that will direct the address operand into this if-clause.

Member TDGen::writeScalarToVectorDefs (std::ostream &o) const

Add i8 and i16 subword support once those types have RegisterClass support. For now, just skip generation for them.

Member TPEF::ResourceSection::findResource (ResourceElement::ResourceType aType, HalfWord anId) const

Instance not found exception. After all exceptions are implemented.

Member TPEF::TPEFCodeSectionReader::readInfo (BinaryStream &stream, Section *sect) const

Convert assertion onnstruction encoder identifier into a test with warning or error message.

Member TransportPipeline::startOperation (Operation &op)

This can be optimized a lot.

Member TTAMachine::FUPort::bindingString () const

this should be moved to BaseFUPort.

Member TTAMachine::FUPort::updateBindingString () const

this should be moved to BaseFUPort.

Class TTAProgram::CodeGenerator

Rename to POMGenerator.

Member TTAProgram::CodeGenerator::CodeGenerator (const TTAMachine::Machine &mach)

This should probably take only Program

Member TTAProgram::CodeSnippet::insertBefore (const Instruction &pos, Instruction *ins)

Refactor and share implementation with insertInstructionAfter()

Member TTAProgram::CodeSnippet::instructionAt (UIntWord address) const

Rename to instruction() to match Program::procedure() and Instruction::move().

Member TTAProgram::Procedure::insertBefore (const Instruction &pos, Instruction *ins)

Refactor and share implementation with insertInstructionAfter()

Member TTAProgram::Program::removeProcedure (Procedure &proc)

Copy the deleted CodeLabels to the removed procedure's own Scope objects.

Class TTAProgram::Scope

Implement rest of the Scopes (only GlobalScope is supported currently).

Member TTAProgram::Terminal::hintOperation () const

This should be probably merged with operation() as "hints" are not really useful, we should make sure the operation of the move is known.

Member TTAProgram::TerminalFUPort::operationIndex () const

Rename to operandIndex()?

Member TTAProgram::TPEFProgramFactory::resolveSocketAllocations (std::vector< SocketAllocation > &allocs) const

Yes, we should store the port allocations also to TPEF, if they have been assigned by the scheduler. This kind of resolving again and again does not make sense!

Member TTAProgram::TPEFProgramFactory::seekFunctionStartPoints ()

This function should do code analysis, but for it actually scans symbol sections for code symbol, which are intepret as function start points.

Class VirtRegIndependenceGraph

This approach has at least the following unsolved problems: