56 "interconnection by adding separate RF for each distinct bus width.");
63 "Short immediate width for each bus.");
65 "Number of dummy buses for long immediates. (power-of-2)");
67 "Generate a VLIW-style register file.");
82 virtual std::vector<RowID>
86 std::vector<RowID> result;
98 std::ostringstream msg(std::ostringstream::out);
100 <<
"Error loading the adf." << std::endl;
110 for (
int i = 0; i < rfNavi.
count(); i++) {
112 if (rf->
width() == 1) {
120 for (
int i = 0; i < rfNavi.
count(); i++) {
122 if (rf->
width() != 1) {
132 for (
int i = 0; i < socketNavi.
count(); i++) {
133 if (socketNavi.
item(i)->portCount() == 0 ) {
145 std::vector<int>::iterator iter;
147 for (
int i = 0; i < socketNavi.
count(); i++) {
170 std::vector<Socket::Direction> directions;
171 std::vector< std::vector<int> > readSockets(numDistinctBusWidths),
172 writeSockets(numDistinctBusWidths),
173 controlSockets(numDistinctBusWidths);
175 for (
int i = 0; i < socketNavi.
count(); i++) {
178 directions.push_back(dir);
186 &&
dynamic_cast<ControlUnit*
>(parentUnit) == NULL) {
188 readSockets[widx].push_back(i);
191 writeSockets[widx].push_back(i);
195 controlSockets[widx].push_back(i);
203 for (
int i = 0; i < busNavi.
count(); i++) {
209 std::vector< std::vector<int> > readBuses(numDistinctBusWidths),
210 writeBuses(numDistinctBusWidths);
213 for (
int widx = 0; widx < numDistinctBusWidths; ++widx) {
219 for (
unsigned int i = 0; i < controlSockets[widx].size(); i++) {
220 int idx = controlSockets[widx][i];
222 socketNavi.
item(idx)->setDirection(directions[idx]);
224 readBuses[widx].push_back(busCount);
225 writeBuses[widx].push_back(busCount++);
228 for (
unsigned int i = 0; i < readSockets[widx].size(); i++) {
229 int idx = readSockets[widx][i];
232 socketNavi.
item(idx)->setDirection(directions[idx]);
233 readBuses[widx].push_back(busCount++);
236 for (
unsigned int i = 0; i < writeSockets[widx].size(); i++) {
237 int idx = writeSockets[widx][i];
240 socketNavi.
item(idx)->setDirection(directions[idx]);
241 writeBuses[widx].push_back(busCount++);
246 for (
int widx = 0; widx < numDistinctBusWidths; ++widx) {
247 if (readBuses[widx].size() == 0 && writeBuses[widx].size() == 0) {
258 readBuses[widx].size(),
259 writeBuses[widx].size(),
265 for (
unsigned int i = 0; i < readBuses[widx].size(); i++) {
273 busNavi.
item(readBuses[widx][i])->segment(0)->
274 attachSocket(*newSocket);
279 for (
unsigned int i = 0; i < writeBuses[widx].size(); i++) {
287 busNavi.
item(writeBuses[widx][i])->segment(0)->
288 attachSocket(*newSocket);
295 for (
int widx = 0; widx < numDistinctBusWidths; ++widx) {
296 for (
unsigned int i = 0; i < writeSockets[widx].size(); i++) {
297 Socket* output = socketNavi.
item(writeSockets[widx][i]);
298 for (
unsigned int j = 0; j < readBuses[widx].size(); j++) {
299 Bus* readBus = busNavi.
item(readBuses[widx][j]);
305 for (
int i = 0; i < busNavi.
count(); i++) {
315 for (
int i = 0; i < busNavi.
count(); i++) {
352 result.push_back(confID);
#define assert(condition)
int RowID
Type definition of row ID in relational databases.
#define EXPORT_DESIGN_SPACE_EXPLORER_PLUGIN(PLUGIN_NAME__)
find Finds info of the inner loops in the false
static std::ostream & errorStream()
static std::string toString(const T &source)
RowID addArchitecture(const TTAMachine::Machine &mom)
TTAMachine::Machine * architecture(RowID id) const
MachineConfiguration configuration(RowID id) const
RowID addConfiguration(const MachineConfiguration &conf)
void readOptionalParameter(const std::string paramName, T ¶m) const
void addParameter(TCEString name, ExplorerPluginParameterType type, bool compulsory=true, TCEString defaultValue="", TCEString description="")
virtual DSDBManager & db()
virtual int width() const
virtual RFPort * port(const std::string &name) const
virtual Segment * segment(int index) const
virtual void setImmediateWidth(int width)
virtual TCEString name() const
virtual void addSlot(const std::string &slotName, int width, ImmediateUnit &dstUnit)
ComponentType * item(int index) const
virtual RegisterFileNavigator registerFileNavigator() const
virtual InstructionTemplateNavigator instructionTemplateNavigator() const
virtual void deleteInstructionTemplate(InstructionTemplate &instrTempl)
virtual SocketNavigator socketNavigator() const
virtual void removeBus(Bus &bus)
virtual ImmediateUnitNavigator immediateUnitNavigator() const
virtual BusNavigator busNavigator() const
virtual void addBus(Bus &bus)
virtual void addRegisterFile(RegisterFile &unit)
virtual void removeSocket(Socket &socket)
virtual void addSocket(Socket &socket)
virtual void removeRegisterFile(RegisterFile &unit)
virtual Socket * outputSocket() const
virtual void attachSocket(Socket &socket)
virtual int width() const =0
Unit * parentUnit() const
@ NORMAL
Used for general register allocation.
void attachSocket(Socket &socket)
void setDirection(Direction direction)
@ OUTPUT
Data goes from port to bus.
@ INPUT
Data goes from bus to port.
bool isConnectedTo(const Bus &bus) const
Direction direction() const
Port * port(int index) const
void attachBus(Segment &bus)
virtual bool producesArchitecture() const
virtual bool requiresApplication() const
virtual std::vector< RowID > explore(const RowID &configurationID, const unsigned int &)
static const TCEString wipeRegisterFilePN_
virtual bool requiresSimulationData() const
int longImmediateBusCount_
std::vector< int > distinctBusWidths_
static const TCEString shortImmediateWidthPN_
static const TCEString longImmediateBusCountPN_
int widthIndex(int width)
virtual bool requiresStartingPointArchitecture() const
TTAMachine::Segment * createBus(TTAMachine::Machine *mach, int width)
PLUGIN_DESCRIPTION("Arranges architecture FUs into a VLIW-like " "interconnection by adding separate RF for each distinct bus width.")
virtual bool requiresHDB() const