45#include "boost/regex.hpp"
46#include "boost/format.hpp"
134 const std::string&
name) :
180 delay = sourceDelay + busDelay + destinationDelay;
182#ifdef DEBUG_DELAY_ESTIMATION
185 <<
"," << path.
bus().
name() <<
","
187 <<
"delays={" << sourceDelay <<
"," << busDelay <<
","
188 << destinationDelay <<
"} = " << delay << std::endl;
229 std::string socketName =
"";
237 for (
int i = 0; i < socketNav.
count(); ++i) {
241 socketName =
"input_sub_socket";
243 socketName =
"output_sub_socket";
253 FanInFanOutCombinationSet::const_iterator iter =
254 parameterSet.begin();
255 std::string socketNameCopy = socketName;
256 for (; iter != parameterSet.end(); iter++) {
257 socketName = socketNameCopy +
" " +
267 std::set<std::string>::iterator iter =
270 std::cerr <<
"Warning: Could not get area data "
272 << socketName <<
"' from HDB: "
273 << hdb.
fileName() <<
". Area of this "
274 <<
"socket not counted to total."
285 std::string(
"Could not get socket area data '") +
286 socketName +
"' from HDB: " + hdb.
fileName() +
291 std::string busName =
"";
299 for (
int i = 0; i < busNav.
count(); ++i) {
304 FanInFanOutCombinationSet::const_iterator iter =
305 parameterSet.begin();
306 for (; iter != parameterSet.end(); iter++) {
307 busName =
"sub_bus " +
317 std::set<std::string>::iterator iter =
320 std::cerr <<
"Warning: Could not get area data "
322 << busName <<
"' from HDB: "
323 << hdb.
fileName() <<
". Area of this "
324 <<
"bus not counted to total."
335 std::string(
"Could not get bus area data '") +
336 busName +
"' from HDB. " + hdb.
fileName() +
365 std::string socketName =
"";
371 for (
int i = 0; i < socketNav.
count(); ++i) {
375 socketName =
"input_sub_socket";
377 socketName =
"output_sub_socket";
387 FanInFanOutCombinationSet::const_iterator iter =
388 parameterSet.begin();
389 std::string socketNameCopy = socketName;
390 for (; iter != parameterSet.end(); iter++) {
391 socketName = socketNameCopy +
" " +
414 activeEnergy*activeCycles;
419 idleEnergy*idleCycles;
422 totalIdleEnergy + totalActiveEnergy;
423 energy += totalEnergy;
424#ifdef DEBUG_ENERGY_ESTIMATION
426 <<
"socket " << socket.
name() <<
", subsocket "
427 << socketName <<
": "
428 <<
"active energy = " << activeEnergy
429 <<
" mJ/cycle * " << activeCycles <<
" cycle = "
430 << totalActiveEnergy <<
", "
431 <<
"idle energy = " << idleEnergy
432 <<
" mJ/cycle * " << idleCycles <<
" cycle = "
433 << totalIdleEnergy <<
" TOTAL = " << totalEnergy
440 std::string(
"Could not get socket area data '") +
444 std::string busName =
"";
449 for (
int i = 0; i < busNav.
count(); ++i) {
454 FanInFanOutCombinationSet::const_iterator iter =
455 parameterSet.begin();
456 for (; iter != parameterSet.end(); iter++) {
457 busName =
"sub_bus " +
480 activeEnergy*activeCycles;
485 idleEnergy*idleCycles;
488 totalIdleEnergy + totalActiveEnergy;
489 energy += totalEnergy;
490#ifdef DEBUG_ENERGY_ESTIMATION
492 <<
"bus " << bus.
name() <<
", subbus "
494 <<
"active energy = " << activeEnergy
495 <<
" mJ/cycle * " << activeCycles <<
" cycle = "
496 << totalActiveEnergy <<
", "
497 <<
"idle energy = " << idleEnergy
498 <<
" mJ/cycle * " << idleCycles <<
" cycle = "
499 << totalIdleEnergy <<
" TOTAL = " << totalEnergy
506 std::string(
"Could not get bus energy data '") + busName +
524 std::string socketName =
"";
527 socketName =
"input_sub_socket";
529 socketName =
"output_sub_socket";
538 FanInFanOutCombinationSet::const_iterator iter =
539 parameterSet.begin();
540 std::string socketNameCopy = socketName;
541 for (; iter != parameterSet.end(); iter++) {
542 socketName = socketNameCopy +
" " +
547 (*iter).fanIn == 1 && (*iter).fanOut == 1) {
558 std::set<std::string>::iterator iter =
561 std::cerr <<
"Warning: Could not get throughput delay "
563 << socketName <<
"' from HDB: "
564 << hdb.
fileName() <<
". This value is "
565 <<
"not counted to total." << std::endl;
573 std::string(
"Cannot fetch socket delay data '") +
585 std::string busName =
"";
589 FanInFanOutCombinationSet::const_iterator iter =
590 parameterSet.begin();
591 for (; iter != parameterSet.end(); iter++) {
592 busName =
"sub_bus " +
605 std::set<std::string>::iterator iter =
608 std::cerr <<
"Warning: Could not get throughput delay "
610 << busName <<
"' from HDB: "
611 << hdb.
fileName() <<
". This value is "
612 <<
"not counted to total." << std::endl;
620 std::string(
"Cannot fetch bus delay data '") +
642 std::string entry =
"delay_subsocket_reference";
657 std::string(
"Cannot fetch socket delay data '") +
683 std::string(
"Cannot fetch bus delay data. ") +
702 const std::string& keyName,
const std::string& keyValuePairString) {
703 boost::smatch parsed;
705 (boost::format(
"(.*)(%s)=([^\\s]*)(.*)") % keyName).str());
706 if (!regex_match(keyValuePairString, parsed, regexp)) {
709 "Key not found in value string.");
711 if (parsed.size() < 3)
737 std::vector<std::size_t>& inputWidths,
738 std::vector<std::size_t>& outputWidths) {
740 std::sort(inputWidths.begin(), inputWidths.end());
741 std::sort(outputWidths.begin(), outputWidths.end());
743 std::set<std::size_t> allWidthsTemp;
745 inputWidths.begin(), inputWidths.end(),
746 std::insert_iterator<std::set<std::size_t> >(
747 allWidthsTemp, allWidthsTemp.begin()));
749 outputWidths.begin(), outputWidths.end(),
750 std::insert_iterator<std::set<std::size_t> >(
751 allWidthsTemp, allWidthsTemp.begin()));
752 std::vector<std::size_t> allWidths;
754 allWidthsTemp.begin(), allWidthsTemp.end(),
755 std::insert_iterator<std::vector<std::size_t> >(
756 allWidths, allWidths.begin()));
760 for (std::vector<std::size_t>::iterator i = allWidths.begin();
761 i != allWidths.end(); ++i) {
763 const unsigned int width = *i;
766 std::size_t fanIn = 0;
767 for (
unsigned int n = 0; n < inputWidths.size(); n++) {
769 if (width > inputWidths.at(n) && inputWidths.at(n) > 0)
771 if (inputWidths.at(n) != 0) {
777 std::size_t fanOut = 0;
778 for (
unsigned int n = 0; n < outputWidths.size(); n++) {
780 if (width > outputWidths.at(n) && outputWidths.at(n) > 0)
782 if (outputWidths.at(n) != 0) {
787 if (fanIn == 0 || fanOut == 0)
790 parameters.
fanIn = fanIn;
791 parameters.
fanOut = fanOut;
793 combinations.push_back(parameters);
795 for (
unsigned int n = 0; n < inputWidths.size(); n++) {
796 if (inputWidths.at(n) > width) {
797 inputWidths.at(n) = inputWidths.at(n) - width;
799 inputWidths.at(n) = 0;
802 for (
unsigned int n = 0; n < outputWidths.size(); n++) {
803 if (outputWidths.at(n) > width) {
804 outputWidths.at(n) = outputWidths.at(n) - width;
806 outputWidths.at(n) = 0;
810 for (
unsigned int n = 0; n < allWidths.size(); n++) {
811 if (allWidths.at(n) > width) {
812 allWidths.at(n) = allWidths.at(n) - width;
834 std::vector<std::size_t> inputWidths;
835 std::vector<std::size_t> outputWidths;
841 for (
int i = 0; i < socket.
portCount(); i++) {
842 outputWidths.push_back(socket.
port(i)->
width());
848 for (
int i = 0; i < socket.
portCount(); i++) {
849 inputWidths.push_back(socket.
port(i)->
width());
865 std::vector<std::size_t> inputWidths;
866 std::vector<std::size_t> outputWidths;
870 for (
int i = 0; i < socketNav.
count(); ++i) {
873 std::size_t width = 0;
874 for (
int port = 0; port < socket.
portCount(); port++) {
875 if (
static_cast<unsigned int>(
884 inputWidths.push_back(width);
886 outputWidths.push_back(width);
899using namespace ProGe;
918 "Generates the IC as as an AND-OR network.";
941 "Generates wires to the internal hardware debugger if "
943 +
"', and to the external debugger if the value is '"
945 "for softreset and break, are added if the value is '"
949 "Generates code that prints bus trace if the value is '" +
953 "The first cycle for which the bus trace is printed.");
956 "Generates code that prints global lock trace if the value is"
961 "The first cycle for which the global lock trace is printed. "
966 "-1 delay slot by removing instruction fetch register. "
1015 "rv32_microcode_wrapper",
"rv32_microcode_wrapper_i");
1049 "instruction_in",
"IMEMWIDTHINMAUS*IMEMMAUWIDTH",
BIT_VECTOR,
1052 netlist.
connect(*microCodeImmOut, *decoderRISCVSimmPort);
1094 netlist.
connect(*rvJumpPortMicroCode, *rvJumpPortIfetch);
1095 netlist.
connect(*rvAuipcPortMicroCode, *rvAuipcPortIfetch);
1096 netlist.
connect(*rvOffsetPortMicroCode, *rvOffsetPortIfetch);
1098 netlist.
connect(*ifetchStallPortMicroCode, *ifetchStallPortIFetch);
1104 "Entered debugger connection generation without cause.");
1113 bool is_external =
false, is_internal =
false, is_minimal =
false;
1125 for (std::size_t i = 0; i < toplevelBlock.
subBlockCount(); i++) {
1126 icBlock = &toplevelBlock.
subBlock(i);
1148 if (is_minimal || is_external) {
1156 decoderBlock->
port(
"lock_req");
1159 *dbGlockReqPort, *decoderGlockReqPort, 0, bit, 1);
1165 *ifetchDebugResetPort);
1170 *ifetchDebugLockRqPort);
1176 *ifetchCyclecountPort, *ttaCyclecountPort);
1181 *ifetchLockcountPort, *ttaLockcountPort);
1199 *icBustracePort, *ttaBustracePort);
1203 "db_pc_next",
"IMEMADDRWIDTH",
1217 }
else if (is_internal) {
1219 "db_bp_ena",
"1+db_breakpoints",
1222 "bp_target_cc",
"db_breakpoints_cc*db_data_width",
1225 "bp_target_pc",
"db_breakpoints_pc*IMEMADDRWIDTH",
1229 "db_bp_hit",
"2+db_breakpoints",
1232 "db_tta_continue",
"1",
BIT,
ProGe::IN, toplevelBlock);
1234 "db_tta_forcebreak",
"1",
BIT,
ProGe::IN, toplevelBlock);
1236 "db_tta_stdoutbreak",
"1",
BIT,
ProGe::IN, toplevelBlock);
1250 *dbsmClkPort, generator.
clkPort(toplevelBlock));
1255 *dbsmNresetPort, generator.
rstPort(toplevelBlock));
1258 "bp_ena",
"1+db_breakpoints",
1263 "bp_target_cc",
"db_breakpoints_cc*cyclecnt_width_g",
1273 "bp_target_pc",
"db_breakpoints_pc*IMEMADDRWIDTH",
1284 *ttaContinuePort, *dbsmContinuePort);
1289 *dbsmForceBreakPort);
1294 *ttaStdoutBreakPort, *dbsmStdoutBreakPort);
1297 "bp_hit",
"2+db_breakpoints",
1304 *toplevelBlock.
port(
"busy"), *dbsmExtlockPort);
1312 decoderBlock->
port(
"lock_req");
1315 *dbsmGlockReqPort, *decoderGlockReqPort, 0, bit, 1);
1321 *ifetchDebugLockRqPort);
1325 *ifetchDebugResetPort);
1339 *ifetchPCNextPort, *dbsmPCNextPort);
1344 *ifetchCyclecountPort, *ttaCyclecountPort);
1346 *ifetchCyclecountPort, *dbsmCyclecountPort);
1351 *ifetchLockcountPort, *ttaLockcountPort);
1353 "db_instr",
"IMEMWIDTHINMAUS*IMEMMAUWIDTH",
1356 fetchBlock->
port(
"fetchblock");
1358 *ifetchFetchblockPort, *ttaInstrPort);
1364 NetlistPort* decoderDBResetPort = decoderBlock->
port(
"db_tta_nreset");
1366 toplevelBlock.
netlist().
connect(*ttaResetPort, *decoderDBResetPort);
1402 HDL language,
const std::string& dstDirectory,
1405 const std::string& entityString) {
1418 "ifetch-stall-cond",
1421 "ifetch-stall-port-declarations",
1428 microCodeGen->
generateRTL(instantiator, dstDirectory);
1444 "db-signal-declarations",
1446 std::string(
"no_debug_signal_declaration.snippet"));
1450 if (language ==
VHDL) {
1452 "sync_reset_g",
"boolean",
"true");
1456 "update-condition",
"always@(posedge clk)");
1459 if (language ==
VHDL) {
1461 "sync-waitlist",
"clk, rstx");
1465 "always@(posedge clk or negedge rstx)");
1471 if (language ==
VHDL) {
1473 "no_glock_loopback_g",
"std_logic",
"'1'");
1478 std::size_t reqOpcodeWidth =
1484 "default-instr-reg-write",
1487 std::string(
"default-instr-reg-write.snippet")));
1490 std::string sensitivityStringPCBypassed =
1491 "pc_in, pc_reg, increased_pc ";
1492 std::string sensitivityStringPCNotBypassed =
"";
1494 sensitivityStringPCBypassed +=
",\n pc_load, pc_opcode";
1496 "pc-sensitivity-list-pc-bypass", sensitivityStringPCBypassed);
1499 std::string conditionString =
1500 "pc_load = '1' and ((unsigned(pc_opcode) = IFE_CALL or \n"
1501 " unsigned(pc_opcode) = IFE_JUMP))\n";
1503 "not-bypassed-next-pc-condition", conditionString);
1506 if (language !=
VHDL) {
1507 std::string errorMsg =
1508 "Language not set to VHDL when HW debugger is in "
1514 "debug_logic_g",
"boolean",
"true");
1518 "db-port-declarations",
1522 "debug_minimal_port_declaration.snippet")));
1524 "db-signal-declarations",
1528 "debug_minimal_signal_declaration.snippet")));
1531 "db-port-declarations",
1534 std::string(
"debug_port_declaration.snippet")));
1536 "db-signal-declarations",
1539 std::string(
"debug_signal_declaration.snippet")));
1542 templateDir +
DS +
"ifetch." +
1543 (language ==
VHDL ?
"vhdl" :
"v") +
".tmpl",
1545 std::string(
"ifetch.") +
1546 (language ==
VHDL ?
"vhdl" :
"v"));
1549 templateDir +
DS +
"ifetch." +
1550 (language ==
VHDL ?
"vhdl" :
"v") +
".tmpl",
1552 std::string(
"ifetch.") +
1553 (language ==
VHDL ?
"vhdl" :
"v"));
1560 if (language !=
VHDL) {
1561 std::string errorMsg =
1562 "Instruction register bypass is not supported for "
1578 if (language !=
VHDL) {
1579 std::string errorMsg =
1580 "Language not set to VHDL when HW debugger is in use.";
1588 templateDir +
DS +
"rv32_ifetch.vhdl.tmpl", dstDirectory,
1592 templateDir +
DS +
"ifetch.vhdl.tmpl", dstDirectory,
1603 virtual std::set<int>
1619 if (specifiedDelaySlots != requiredDelaySlots) {
1622 TCEString(
"Decoder generator supports ") +
1624 "-stage transport pipeline of GCU with given options. "
1625 "Given machine has " +
1644 pkgStream <<
" -- instruction width" << endl
1645 <<
" constant INSTRUCTIONWIDTH : positive := "
1648 pkgStream <<
"// instruction width" << endl
1649 <<
"parameter INSTRUCTIONWIDTH = " <<
bem().
width()
1800 switch (direction) {
1809 return std::string();
1821 for (
int i = 0; i < ports; i++) {
1823 if (port->
width() > width) {
1824 width = port->
width();
1839 "Instruction register by pass only implemented for RISC-V");
1844 "addInstructionRegisterBypass(): "
1845 "debugger does not support Instruction Register Bypass "
1852 "bypass_fetchblock_register",
"boolean",
"true");
1857 "Verilog version of instruction register bypass "
1858 "not implemented.");
1860 assert(
false &&
"Unknown HDL choice.");
#define abortWithError(message)
#define assert(condition)
const std::string GENERATE_DEBUGGER_PARAM_MINIMAL
const std::string GENERATE_BUS_TRACE_PARAM
const std::string GENERATE_LOCK_TRACE_PARAM_YES
const std::string RISCV_SIMM_PORT_OUT_NAME
const std::string NO_SELF_LOCKING_PARAM_YES
const std::string BUS_TRACE_STARTING_CYCLE
const std::string ENABLE_FEATURE
const std::string GENERATE_DEBUGGER_PARAM
const std::string GENERATE_DEBUGGER_PARAM_EXTERNAL
const std::string BYPASS_FETCHBLOCK_REG_PARAM_YES
const std::string GENERATE_DEBUGGER_PARAM_YES
const std::string GENERATE_LOCK_TRACE_PARAM
const std::string LOCK_TRACE_STARTING_CYCLE
const std::string PLUGIN_DESCRIPTION
const std::string SYNC_RESET
const std::string BYPASS_FETCHBLOCK_REG_PARAM
const std::string GENERATE_DEBUGGER_PARAM_INTERNAL
const std::string NO_SELF_LOCKING_PARAM
const std::string IFETCH_STALL_PORT_NAME
const std::string GENERATE_BUS_TRACE_PARAM_YES
IDF::MachineImplementation * implementation
the implementation definition of the estimated processor
TTAMachine::Machine * machine
the architecture definition of the estimated processor
#define EXPORT_ICDEC_ESTIMATOR(PLUGIN_NAME__)
#define EXPORT_ICDEC_GENERATOR(PLUGIN_NAME__)
CycleCount ClockCycleCount
Alias for ClockCycleCount.
virtual int width(const TCEString &templateName) const
static std::string toString(const T &source)
static unsigned int toUnsignedInt(const T &source)
virtual std::string name() const
std::string name_
the name of the plugin class in the HDB; used to identify cost data
const TTAMachine::Bus & bus() const
const TTAMachine::Socket & sourceSocket() const
const TTAMachine::Socket & destinationSocket() const
virtual std::string stringValue() const
virtual double doubleValue() const
virtual void setString(std::string value)
virtual int integerValue() const
void setGenerateBusEnable(bool value)
int glockRequestWidth() const
void completeDecoderBlock(const ProGe::NetlistGenerator &nlGenerator, ProGe::NetlistBlock &coreBlock)
static const std::string RISCV_SIMM_PORT_IN_NAME
void setSyncReset(bool value)
void SetHDL(ProGe::HDL language)
void setLockTraceStartingCycle(unsigned int startCycle)
void verifyCompatibility() const
static const std::string GLOCK_PORT_NAME
void generateInstructionDecoder(const ProGe::NetlistGenerator &nlGenerator, const std::string &dstDirectory)
std::set< int > requiredRFLatencies(const TTAMachine::ImmediateUnit &iu) const
void setGenerateLockTrace(bool generate)
void setGenerateNoLoopbackGlock(bool generate)
void setGenerateDebugger(bool generate)
virtual bool estimateICEnergy(HDB::HDBRegistry &hdbRegistry, const TTAMachine::Machine &machine, const IDF::MachineImplementation &machineImplementation, const TTAProgram::Program &, const ExecutionTrace &traceDB, EnergyInMilliJoules &energy)
DefaultICDecoderEstimator(const std::string &name)
DelayInNanoSeconds delayOfSocket(HDB::HDBManager &hdb, const TTAMachine::Socket &socket)
DelayInNanoSeconds delayOfBus(HDB::HDBRegistry &hdbRegistry, const IDF::BusImplementationLocation &implementation)
FanInFanOutCombinationSet socketParameters(const TTAMachine::Socket &socket)
std::vector< ICParameters > FanInFanOutCombinationSet
DelayInNanoSeconds delayOfSocket(HDB::HDBRegistry &hdbRegistry, const IDF::SocketImplementationLocation &implementation)
virtual bool estimateICArea(HDB::HDBRegistry &hdbRegistry, const TTAMachine::Machine &machine, const IDF::MachineImplementation &machineImplementation, AreaInGates &area)
FanInFanOutCombinationSet busParameters(const TTAMachine::Bus &bus)
std::set< std::string > missingComponents_
Set for component names that are missing from HDB.
DataObject valueFromKeyValuePairString(const std::string &keyName, const std::string &keyValuePairString)
DelayInNanoSeconds delayOfBus(HDB::HDBManager &hdb, const TTAMachine::Bus &bus)
FanInFanOutCombinationSet generateFanInFanOutCombinations(std::vector< std::size_t > &inputWidths, std::vector< std::size_t > &outputWidths)
virtual ~DefaultICDecoderEstimator()
virtual bool estimateICDelayOfPath(HDB::HDBRegistry &hdbRegistry, const TransportPath &path, const IDF::MachineImplementation &machineImplementation, const IDF::SocketImplementationLocation &, const IDF::BusImplementationLocation &, const IDF::SocketImplementationLocation &, DelayInNanoSeconds &delay)
bool generateBusTrace() const
virtual void generate(HDL language, const std::string &dstDirectory, const NetlistGenerator &generator, const IDF::MachineImplementation &implementation, const std::string &entityString)
const BinaryEncoding & bem_
bool generateNoSelfLockingFUs() const
DefaultICGenerator * icGenerator_
virtual void verifyCompatibility() const
bool generateLockTrace() const
bool generateDebugger(bool minimal=true) const
int busTraceStartingCycle() const
int lockTraceStartingCycle() const
void generateDebuggerCode(const NetlistGenerator &generator)
virtual void completeNetlist(NetlistBlock &netlistBlock, const NetlistGenerator &generator)
void addDummyIfetchDebugPorts(const NetlistGenerator &generator)
static std::string vhdlDirection(ProGe::Direction direction)
virtual ~DefaultICDecoderGenerator()
DefaultICDecoderGenerator(const TTAMachine::Machine &machine, const BinaryEncoding &bem)
static int dataPortWidth(const TTAMachine::Socket &socket)
bool bypassInstructionRegister() const
void addInstructioRegisterBypass(HDL language, const NetlistGenerator &generator)
virtual std::set< int > requiredRFLatencies(const TTAMachine::ImmediateUnit &iu) const
DefaultDecoderGenerator * decoderGenerator_
int calculateSupportedDelaySlots() const
const TTAMachine::Machine & ttamachine_
virtual void writeGlobalDefinitions(HDL language, std::ostream &pkgStream) const
bool hasSynchronousReset() const
void addRV32MicroCode(NetlistBlock &netlistBlock, const NetlistGenerator &generator)
void verifyCompatibility() const
void setBusTraceStartingCycle(unsigned int cycle)
void setGenerateBusTrace(bool generate)
void SetHDL(ProGe::HDL language)
void addICToNetlist(const ProGe::NetlistGenerator &generator, ProGe::NetlistBlock &netlistBlock)
void setExportBustrace(bool export_bt)
void generateInterconnectionNetwork(const std::string &dstDirectory)
static std::string dataDirPath(const std::string &prog)
std::string errorMessage() const
ClockCycleCount simulatedCycleCount() const
ClockCycleCount socketWriteCount(SocketID socket) const
ClockCycleCount busWriteCount(BusID bus) const
static const std::string DIRECTORY_SEPARATOR
std::string fileName() const
virtual DataObject costEstimationDataValue(const std::string &valueName, const std::string &pluginName) const
DataObject socketCostEstimationData(const std::string &valueName, RowID socketID, const std::string &pluginName) const
DataObject busCostEstimationData(const std::string &valueName, RowID busID, const std::string &pluginName) const
CachedHDBManager & hdb(const std::string fileName)
void replacePlaceholderFromFile(const std::string &key, const Path &filePath, bool append=false)
void replacePlaceholder(const std::string &key, const std::string &replacer, bool append=false)
std::string icDecoderHDB() const
TCETools::CIStringSet OperationSet
static OperationSet getOpset(const TTAMachine::Machine &mach)
const std::string & instanceName() const
const std::string & moduleName() const
HDLTemplateInstantiator & getTemplateInstatiator()
void instantiateHDLTemplate(const std::string &srcFile, const std::string &dstDirectory, std::string newName="0")
static size_t gcuOpcodeWidth(const TTAMachine::Machine &mach)
void addParameter(const std::string &name, const std::string &description)
const BinaryEncoding & bem() const
std::string parameterValue(const std::string &name) const
bool hasParameterSet(const std::string &name) const
const TTAMachine::Machine & machine() const
virtual size_t subBlockCount() const
void addSubBlock(BaseNetlistBlock *subBlock, const std::string &instanceName="")
void setParameter(const std::string &name, const std::string &type, const std::string &value)
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
NetlistBlock & subBlock(size_t index) override
void addPackage(const std::string &packageName)
virtual const NetlistBlock & parentBlock() const override
virtual const Netlist & netlist() const
NetlistPort & rstPort(const NetlistBlock &block) const
static const std::string FETCHBLOCK_PORT_NAME
NetlistPort & gcuReturnAddressInPort() const
NetlistBlock & instructionDecompressor() const
NetlistBlock & instructionDecoder() const
NetlistBlock & instructionFetch() const
NetlistPort & clkPort(const NetlistBlock &block) const
const ProGeContext & context() const
void setToStatic(StaticSignal value) const
void setWidthFormula(const std::string &newFormula)
std::string widthFormula() const
bool connect(const NetlistPort &port1, const NetlistPort &port2, int port1FirstBit, int port2FirstBit, int width=1)
void disconnectPorts(const NetlistPort &port1, const NetlistPort &port2)
const TTAMachine::Machine & adf() const
void setBypassInstructionRegister(const bool &value)
void generateRTL(HDLTemplateInstantiator &instantiator, const std::string &fileDst)
@ GND
All port signals set to low.
@ VCC
All port signals set to high.
virtual bool isConnectedTo(const Socket &socket) const
virtual Machine * machine() const
virtual TCEString name() const
ComponentType * item(int index) const
virtual SocketNavigator socketNavigator() const
virtual BusNavigator busNavigator() const
virtual ControlUnit * controlUnit() const
bool isRISCVMachine() const
virtual int width() const =0
@ OUTPUT
Data goes from port to bus.
@ INPUT
Data goes from bus to port.
Direction direction() const
Port * port(int index) const
Segment * segment(int index) const
double AreaInGates
type for area values in equivalent gates
double DelayInNanoSeconds
type for propagation delays in nano seconds
double EnergyInMilliJoules
type for consumed energy in milli joules
@ BIT_VECTOR
Several bits.
Direction
Direction of the port.
@ BIDIR
Bidirectional port.
HDL
HDLs supported by ProGe.