OpenASIP 2.2
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Public Member Functions | Protected Member Functions | Private Member Functions | Private Attributes | Static Private Attributes | List of all members
AlmaIFIntegrator Class Reference

#include <AlmaIFIntegrator.hh>

Inheritance diagram for AlmaIFIntegrator:
Inheritance graph
Collaboration diagram for AlmaIFIntegrator:
Collaboration graph

Public Member Functions

 AlmaIFIntegrator ()
 
 AlmaIFIntegrator (const TTAMachine::Machine *machine, const IDF::MachineImplementation *idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString entityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType, bool syncReset, bool generateIntegratedTestbench)
 
virtual ~AlmaIFIntegrator ()
 
virtual void integrateProcessor (const ProGe::NetlistBlock *progeBlock)
 
virtual bool integrateCore (const ProGe::NetlistBlock &cores, int coreId)
 
virtual void printInfo (std::ostream &stream) const
 
virtual TCEString deviceFamily () const
 
virtual void setDeviceFamily (TCEString devFamily)
 
virtual TCEString devicePackage () const
 
virtual TCEString deviceSpeedClass () const
 
virtual int targetClockFrequency () const
 
virtual TCEString pinTag () const
 
virtual bool chopTaggedSignals () const
 
virtual ProjectFileGenerator * projectFileGenerator () const
 
- Public Member Functions inherited from PlatformIntegrator
 PlatformIntegrator ()
 
 PlatformIntegrator (const TTAMachine::Machine *machine, const IDF::MachineImplementation *idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString coreEntityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)
 
virtual ~PlatformIntegrator ()
 
void setDeviceName (TCEString devName)
 
TCEString deviceName () const
 
const ProGe::NetlistBlock & progeBlock () const
 
const ProGe::NetlistBlock & toplevelBlock () const
 
void setSharedOutputDir (const TCEString &sharedDir)
 
TCEString outputPath () const
 
TCEString outputFilePath (TCEString fileName, bool absolute=false) const
 
TCEString coreEntityName () const
 
const TTAMachine::Machine * machine () const
 
const IDF::MachineImplementation * idf () const
 
const MemInfo & imemInfo () const
 
const MemInfo & dmemInfo (TTAMachine::AddressSpace *as) const
 
const MemInfo & dmemInfo (int index) const
 
int dmemCount () const
 
ProGe::NetlistPort * clockPort () const
 
ProGe::NetlistPort * resetPort () const
 

Protected Member Functions

virtual MemoryGenerator & imemInstance (MemInfo imem, int coreId)
 
virtual MemoryGenerator & dmemInstance (MemInfo dmem, TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
 
- Protected Member Functions inherited from PlatformIntegrator
ProGe::NetlistBlock * integratorBlock ()
 
virtual void initPlatformNetlist (const ProGe::NetlistBlock *progeBlock)
 
virtual void connectToplevelPort (const ProGe::NetlistPort &corePort, const TCEString signalPrefix="")
 
virtual bool hasPinTag (const TCEString &signal) const
 
void copyProgeBlockToNetlist (const ProGe::NetlistBlock *progeBlock)
 
virtual bool createMemories (int coreId)
 
virtual bool generateMemory (MemoryGenerator &memGen, std::vector< TCEString > &generatedFiles, int memIndex, int coreId)
 
virtual void writeNewToplevel ()
 
void addProGeFiles () const
 
TCEString programName () const
 
TCEString progeFilePath (TCEString fileName, bool absolute=false) const
 
TCEString tbFilePath (TCEString fileName, bool absolute=false) const
 
TCEString chopSignalToTag (const TCEString &original, const TCEString &tag) const
 
void progeOutputHdlFiles (std::vector< TCEString > &files) const
 
std::ostream & warningStream () const
 
std::ostream & errorStream () const
 
TCEString platformEntityName () const
 
void parseDataMemories ()
 
void clearDataMemories ()
 
MemInfo readLsuParameters (const TTAMachine::FunctionUnit &lsu)
 

Private Member Functions

void addMemoryPorts (const TCEString as_name, int data_width, int addr_width, const bool isShared, const bool overrideAsWidth)
 
void addMemoryPorts (const TCEString as_name, int mem_count, int data_width, int addr_width, int strb_width, const bool overrideAsWidth)
 
void initAlmaifBlock ()
 
void addAlmaifFiles ()
 
void copyPlatformFile (const TCEString inputPath, std::vector< TCEString > &fileList, bool isScript=false) const
 
TCEString axiAddressWidth () const
 
void findMemories ()
 
void exportUnconnectedPorts (int coreId)
 
void connectCoreMemories (MemInfo mem, TCEString mem_name, TCEString mem_block_name, bool seconds)
 
void addPortToGroup (ProGe::NetlistPortGroup *port_group, const ProGe::Direction dir, const TCEString name, const TCEString width)
 
void addPortToAlmaIFBlock (const TCEString name, const TCEString width, const ProGe::Direction dir, const TCEString core_name="")
 
void addPortToAlmaIFBlock (const TCEString name, const int width, const ProGe::Direction dir, const TCEString core_name="")
 
void generateIntegratedTestbench ()
 
ProGe::NetlistPortGroup * axiSlavePortGroup ()
 
ProGe::NetlistPortGroup * axiMasterPortGroup ()
 

Private Attributes

MemoryGenerator * imemGen_
 
std::map< TCEString, MemoryGenerator * > dmemGen_
 
std::map< TCEString, ProGe::NetlistPort * > almaif_ttacore_ports
 
ProGe::NetlistBlock * almaifBlock_
 
TCEString deviceFamily_
 
TCEString deviceName_
 
DefaultProjectFileGenerator * fileGen_
 
MemInfo dmemInfo_
 
MemInfo pmemInfo_
 
bool secondDmem_
 
bool secondPmem_
 
bool dmemHandled_
 
bool pmemHandled_
 
std::string secondDmemName_
 
int secondDmemDataw_ = 0
 
int secondDmemAddrw_ = 0
 
std::string secondPmemName_
 
int secondPmemDataw_ = 0
 
int secondPmemAddrw_ = 0
 
HDLTemplateInstantiator accelInstantiator_
 
bool hasMinimalDebugger_
 
bool hasSeparateLocalMemory_ = true
 
bool syncReset_
 
bool broadcast_pmem_
 
bool dmem_dram_ = false
 
bool imem_dp_ = false
 
bool generateIntegratedTestbench_ = false
 

Static Private Attributes

static const TCEString DMEM_NAME = "data"
 
static const TCEString PMEM_NAME = "param"
 
static const TCEString AXI_AS_NAME = "axi_as"
 
static const TCEString ALMAIF_MODULE = "tta_accel"
 
static const TCEString DEFAULT_DEVICE = "xc7z020clg400-1"
 
static const int DEFAULT_RESERVED_PRIVATE_MEM_SIZE = 2048
 
static const int DEFAULT_LOCAL_MEMORY_WIDTH = 15
 

Additional Inherited Members

- Static Protected Attributes inherited from PlatformIntegrator
static const TCEString TTA_CORE_CLK = "clk"
 
static const TCEString TTA_CORE_RSTX = "rstx"
 

Detailed Description

Definition at line 40 of file AlmaIFIntegrator.hh.

Constructor & Destructor Documentation

◆ AlmaIFIntegrator() [1/2]

AlmaIFIntegrator::AlmaIFIntegrator ( )

Definition at line 61 of file AlmaIFIntegrator.cc.

61 : PlatformIntegrator() {
62}

◆ AlmaIFIntegrator() [2/2]

AlmaIFIntegrator::AlmaIFIntegrator ( const TTAMachine::Machine *  machine,
const IDF::MachineImplementation *  idf,
ProGe::HDL  hdl,
TCEString  progeOutputDir,
TCEString  entityName,
TCEString  outputDir,
TCEString  programName,
int  targetClockFreq,
std::ostream &  warningStream,
std::ostream &  errorStream,
const MemInfo &  imem,
MemType  dmemType,
bool  syncReset,
bool  generateIntegratedTestbench 
)

Definition at line 64 of file AlmaIFIntegrator.cc.

71 : PlatformIntegrator(
72 machine, idf, hdl, progeOutputDir, coreEntityName, outputDir,
73 programName, targetClockFreq, warningStream, errorStream, imem,
74 dmemType),
75 imemGen_(NULL),
76 dmemGen_(),
77 almaifBlock_(NULL),
78 deviceFamily_(""),
79 fileGen_(new DefaultProjectFileGenerator(coreEntityName, this)),
80 secondDmem_(false),
81 secondPmem_(false),
82 dmemHandled_(false),
83 pmemHandled_(false),
84 syncReset_(syncReset),
85 broadcast_pmem_(false),
86 generateIntegratedTestbench_(generateIntegratedTestbench) {
87 if (idf->icDecoderParameterValue("debugger") == "external") {
88 hasMinimalDebugger_ = false;
89 } else if (idf->icDecoderParameterValue("debugger") == "minimal") {
90 hasMinimalDebugger_ = true;
91 } else {
92 TCEString msg =
93 "AlmaIF interface requires connections to an external debugger.";
94 throw InvalidData(__FILE__, __LINE__, "AlmaIFIntegrator", msg);
95 }
96}
AlmaIFIntegrator::dmemGen_
std::map< TCEString, MemoryGenerator * > dmemGen_
Definition AlmaIFIntegrator.hh:126
AlmaIFIntegrator::almaifBlock_
ProGe::NetlistBlock * almaifBlock_
Definition AlmaIFIntegrator.hh:129
AlmaIFIntegrator::imemGen_
MemoryGenerator * imemGen_
Definition AlmaIFIntegrator.hh:125
AlmaIFIntegrator::fileGen_
DefaultProjectFileGenerator * fileGen_
Definition AlmaIFIntegrator.hh:134
IDF::MachineImplementation::icDecoderParameterValue
std::string icDecoderParameterValue(const std::string &name) const
Definition MachineImplementation.cc:1415
PlatformIntegrator::machine
const TTAMachine::Machine * machine() const
Definition PlatformIntegrator.cc:308
PlatformIntegrator::warningStream
std::ostream & warningStream() const
Definition PlatformIntegrator.cc:282
PlatformIntegrator::idf
const IDF::MachineImplementation * idf() const
Definition PlatformIntegrator.cc:315
PlatformIntegrator::programName
TCEString programName() const
Definition PlatformIntegrator.cc:133
PlatformIntegrator::errorStream
std::ostream & errorStream() const
Definition PlatformIntegrator.cc:289
PlatformIntegrator::coreEntityName
TCEString coreEntityName() const
Definition PlatformIntegrator.cc:126

References hasMinimalDebugger_, IDF::MachineImplementation::icDecoderParameterValue(), and PlatformIntegrator::idf().

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◆ ~AlmaIFIntegrator()

AlmaIFIntegrator::~AlmaIFIntegrator ( )
virtual

Definition at line 98 of file AlmaIFIntegrator.cc.

98 {
99
100 if (imemGen_ != NULL) {
101 delete imemGen_;
102 }
103 if (!dmemGen_.empty()) {
104 std::map<TCEString, MemoryGenerator*>::iterator iter =
105 dmemGen_.begin();
106 while (iter != dmemGen_.end()) {
107 delete iter->second;
108 iter++;
109 }
110 }
111}

References dmemGen_, and imemGen_.

Member Function Documentation

◆ addAlmaifFiles()

void AlmaIFIntegrator::addAlmaifFiles ( )
private

Definition at line 827 of file AlmaIFIntegrator.cc.

827 {
828 const std::string DS = FileSystem::DIRECTORY_SEPARATOR;
829 std::vector<TCEString> almaifFiles;
830
831 TCEString basePath = Environment::dataDirPath("ProGe");
832 TCEString platformPath = basePath + DS + "platform" + DS;
833 TCEString dbPath = basePath + DS + "debugger" + DS;
834
835 TCEString outputPath = outputFilePath("tta-accel.vhdl", true);
836 if (pmemInfo_.asAddrw == 32) {
837 Path snippet(platformPath + "axi_master_port_declaration.snippet");
838 accelInstantiator_.replacePlaceholderFromFile(
839 "m-axi-port-declarations", snippet);
840 } else {
841 Path snippet(platformPath + "axi_master_signal_declaration.snippet");
842 accelInstantiator_.replacePlaceholderFromFile(
843 "m-axi-signal-declarations", snippet);
844 }
845
846 accelInstantiator_.instantiateTemplateFile(
847 platformPath + "tta-accel.vhdl.tmpl", outputPath);
848 almaifFiles.push_back(outputPath);
849
850 copyPlatformFile(platformPath + "tta-axislave.vhdl", almaifFiles);
851 copyPlatformFile(platformPath + "almaif_decoder.vhdl", almaifFiles);
852 copyPlatformFile(platformPath + "almaif_axi_arbiter.vhdl", almaifFiles);
853 copyPlatformFile(platformPath + "almaif_mc_arbiter.vhdl", almaifFiles);
854 copyPlatformFile(platformPath + "almaif_axi_expander.vhdl", almaifFiles);
855 copyPlatformFile(platformPath + "membus_splitter.vhdl", almaifFiles);
856 copyPlatformFile(platformPath + "almaif_membus_delay.vhdl", almaifFiles);
857 copyPlatformFile(dbPath + "registers-pkg.vhdl", almaifFiles);
858
859 if (hasMinimalDebugger_) {
860 copyPlatformFile(dbPath + "minidebugger.vhdl", almaifFiles);
861 } else {
862 copyPlatformFile(dbPath + "dbregbank.vhdl", almaifFiles);
863 copyPlatformFile(dbPath + "dbsm-entity.vhdl", almaifFiles);
864 copyPlatformFile(dbPath + "dbsm-rtl.vhdl", almaifFiles);
865 copyPlatformFile(dbPath + "debugger.vhdl", almaifFiles);
866 }
867
868 // Copy synthesis scripts
869 TCEString scriptPath = basePath + DS + "synthesis" + DS;
870 accelInstantiator_.replacePlaceholder("part_name", deviceName());
871 accelInstantiator_.replacePlaceholder(
872 "toplevel_entity", coreEntityName() + "_toplevel");
873 copyPlatformFile(scriptPath + "find_fmax.py", almaifFiles, true);
874 outputPath = progeFilePath("timing.tcl", true);
875 accelInstantiator_.instantiateTemplateFile(
876 scriptPath + "timing.tcl.tmpl", outputPath);
877 outputPath = progeFilePath("utilization.tcl", true);
878 accelInstantiator_.instantiateTemplateFile(
879 scriptPath + "utilization.tcl.tmpl", outputPath);
880
881 for (unsigned int i = 0; i < almaifFiles.size(); i++) {
882 projectFileGenerator()->addHdlFile(almaifFiles.at(i));
883 }
884}
DS
#define DS
Definition LLVMBackend.cc:124
AlmaIFIntegrator::projectFileGenerator
virtual ProjectFileGenerator * projectFileGenerator() const
Definition AlmaIFIntegrator.cc:1162
AlmaIFIntegrator::accelInstantiator_
HDLTemplateInstantiator accelInstantiator_
Definition AlmaIFIntegrator.hh:146
AlmaIFIntegrator::copyPlatformFile
void copyPlatformFile(const TCEString inputPath, std::vector< TCEString > &fileList, bool isScript=false) const
Definition AlmaIFIntegrator.cc:887
Environment::dataDirPath
static std::string dataDirPath(const std::string &prog)
Definition Environment.cc:176
FileSystem::DIRECTORY_SEPARATOR
static const std::string DIRECTORY_SEPARATOR
Definition FileSystem.hh:189
HDLTemplateInstantiator::instantiateTemplateFile
void instantiateTemplateFile(const std::string &templateFile, const std::string &dstFile)
Definition HDLTemplateInstantiator.cc:113
HDLTemplateInstantiator::replacePlaceholderFromFile
void replacePlaceholderFromFile(const std::string &key, const Path &filePath, bool append=false)
Definition HDLTemplateInstantiator.cc:89
HDLTemplateInstantiator::replacePlaceholder
void replacePlaceholder(const std::string &key, const std::string &replacer, bool append=false)
Definition HDLTemplateInstantiator.cc:62
PlatformIntegrator::deviceName
TCEString deviceName() const
Definition PlatformIntegrator.hh:114
PlatformIntegrator::progeFilePath
TCEString progeFilePath(TCEString fileName, bool absolute=false) const
Definition PlatformIntegrator.cc:140
PlatformIntegrator::outputPath
TCEString outputPath() const
Definition PlatformIntegrator.cc:190
PlatformIntegrator::outputFilePath
TCEString outputFilePath(TCEString fileName, bool absolute=false) const
Definition PlatformIntegrator.cc:154
ProjectFileGenerator::addHdlFile
void addHdlFile(const TCEString &file)
Definition ProjectFileGenerator.cc:56

References accelInstantiator_, ProjectFileGenerator::addHdlFile(), MemInfo::asAddrw, copyPlatformFile(), PlatformIntegrator::coreEntityName(), Environment::dataDirPath(), PlatformIntegrator::deviceName(), FileSystem::DIRECTORY_SEPARATOR, DS, hasMinimalDebugger_, HDLTemplateInstantiator::instantiateTemplateFile(), PlatformIntegrator::outputFilePath(), PlatformIntegrator::outputPath(), pmemInfo_, PlatformIntegrator::progeFilePath(), projectFileGenerator(), HDLTemplateInstantiator::replacePlaceholder(), and HDLTemplateInstantiator::replacePlaceholderFromFile().

Referenced by integrateProcessor().

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◆ addMemoryPorts() [1/2]

void AlmaIFIntegrator::addMemoryPorts ( const TCEString  as_name,
int  data_width,
int  addr_width,
const bool  isShared,
const bool  overrideAsWidth 
)
private

Definition at line 788 of file AlmaIFIntegrator.cc.

790 {
791 int mem_count = 1;
792
793 data_width = data_width * mem_count;
794 addr_width = addr_width * mem_count;
795 // In case the data_width has been already multiplied by the mem_count,
796 // we have to undo the multiplication, so the rounding is done properly
797 // for the single memory version and only then multiplied by the
798 // mem_count.
799 int strb_width = (data_width / mem_count + 7) / 8 * mem_count;
800
801 addMemoryPorts(
802 prefix, mem_count, data_width, addr_width, strb_width,
803 overrideAsWidth);
804}
AlmaIFIntegrator::addMemoryPorts
void addMemoryPorts(const TCEString as_name, int data_width, int addr_width, const bool isShared, const bool overrideAsWidth)
Definition AlmaIFIntegrator.cc:788

References addMemoryPorts().

Referenced by addMemoryPorts(), connectCoreMemories(), and initAlmaifBlock().

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◆ addMemoryPorts() [2/2]

void AlmaIFIntegrator::addMemoryPorts ( const TCEString  as_name,
int  mem_count,
int  data_width,
int  addr_width,
int  strb_width,
const bool  overrideAsWidth 
)
private

Definition at line 807 of file AlmaIFIntegrator.cc.

809 {
810 addPortToAlmaIFBlock(prefix + "_avalid_out", mem_count, ProGe::OUT);
811 addPortToAlmaIFBlock(prefix + "_aready_in", mem_count, ProGe::IN);
812 if (overrideAsWidth) {
813 addPortToAlmaIFBlock(
814 prefix + "_aaddr_out", "local_mem_addrw_g", ProGe::OUT);
815 } else {
816 addPortToAlmaIFBlock(prefix + "_aaddr_out", addr_width, ProGe::OUT);
817 }
818 addPortToAlmaIFBlock(prefix + "_awren_out", mem_count, ProGe::OUT);
819 addPortToAlmaIFBlock(prefix + "_astrb_out", strb_width, ProGe::OUT);
820 addPortToAlmaIFBlock(prefix + "_adata_out", data_width, ProGe::OUT);
821 addPortToAlmaIFBlock(prefix + "_rvalid_in", mem_count, ProGe::IN);
822 addPortToAlmaIFBlock(prefix + "_rready_out", mem_count, ProGe::OUT);
823 addPortToAlmaIFBlock(prefix + "_rdata_in", data_width, ProGe::IN);
824}
AlmaIFIntegrator::addPortToAlmaIFBlock
void addPortToAlmaIFBlock(const TCEString name, const TCEString width, const ProGe::Direction dir, const TCEString core_name="")
Definition AlmaIFIntegrator.cc:689
ProGe::OUT
@ OUT
Output port.
Definition ProGeTypes.hh:54
ProGe::IN
@ IN
Input port.
Definition ProGeTypes.hh:53

References addPortToAlmaIFBlock(), ProGe::IN, and ProGe::OUT.

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◆ addPortToAlmaIFBlock() [1/2]

void AlmaIFIntegrator::addPortToAlmaIFBlock ( const TCEString  name,
const int  width,
const ProGe::Direction  dir,
const TCEString  core_name = "" 
)
private

Definition at line 698 of file AlmaIFIntegrator.cc.

700 {
701 NetlistPort* port = new NetlistPort(
702 name, Conversion::toString(width), width, ProGe::BIT_VECTOR, dir,
703 *almaifBlock_);
704 if (core_name != "") almaif_ttacore_ports[core_name] = port;
705}
AlmaIFIntegrator::almaif_ttacore_ports
std::map< TCEString, ProGe::NetlistPort * > almaif_ttacore_ports
Definition AlmaIFIntegrator.hh:127
Conversion::toString
static std::string toString(const T &source)
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition ProGeTypes.hh:48

References almaif_ttacore_ports, almaifBlock_, ProGe::BIT_VECTOR, and Conversion::toString().

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◆ addPortToAlmaIFBlock() [2/2]

void AlmaIFIntegrator::addPortToAlmaIFBlock ( const TCEString  name,
const TCEString  width,
const ProGe::Direction  dir,
const TCEString  core_name = "" 
)
private

Definition at line 689 of file AlmaIFIntegrator.cc.

691 {
692 NetlistPort* port =
693 new NetlistPort(name, width, ProGe::BIT_VECTOR, dir, *almaifBlock_);
694 if (core_name != "") almaif_ttacore_ports[core_name] = port;
695}

References almaif_ttacore_ports, almaifBlock_, and ProGe::BIT_VECTOR.

Referenced by addMemoryPorts(), connectCoreMemories(), and initAlmaifBlock().

◆ addPortToGroup()

void AlmaIFIntegrator::addPortToGroup ( ProGe::NetlistPortGroup *  port_group,
const ProGe::Direction  dir,
const TCEString  name,
const TCEString  width 
)
private

Definition at line 708 of file AlmaIFIntegrator.cc.

710 {
711 ProGe::DataType type = ProGe::BIT_VECTOR;
712 if (width == "1") {
713 type = ProGe::BIT;
714 }
715 NetlistPort* port = new NetlistPort(name, width, type, dir);
716 port_group->addPort(*port);
717}
ProGe::NetlistPortGroup::addPort
void addPort(NetlistPort &port)
Definition NetlistPortGroup.cc:93
ProGe::DataType
DataType
Data types of hardware ports.
Definition ProGeTypes.hh:46
ProGe::BIT
@ BIT
One bit.
Definition ProGeTypes.hh:47

References ProGe::NetlistPortGroup::addPort(), ProGe::BIT, and ProGe::BIT_VECTOR.

Referenced by axiMasterPortGroup(), and axiSlavePortGroup().

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◆ axiAddressWidth()

TCEString AlmaIFIntegrator::axiAddressWidth ( ) const
private

Returns the AXI bus facing address width: 2 bits for address space select

  • maximum of the four address space widths (byte-addressed):
  • CTRL block (fixed 1024 bytes per core)
  • Instruction memory
  • Data and parameter memories

Definition at line 243 of file AlmaIFIntegrator.cc.

243 {
244 // IMEM address width
245 int imemAddressWidth = 0;
246 if (imemInfo().type != VHDL_ARRAY) {
247 imemAddressWidth =
248 MathTools::requiredBits0Bit0(
249 (imemInfo().widthInMaus * imemInfo().mauWidth + 7) / 8 - 1) +
250 imemInfo().portAddrw;
251 }
252 // Debugger address space:
253 int debugAddressWidth = 8;
254 int dmemAddressWidth =
255 dmemInfo_.portAddrw +
256 MathTools::requiredBits0Bit0(
257 std::max(0, dmemInfo_.mauWidth * dmemInfo_.widthInMaus / 8 - 1));
258
259 // Skip param if its width is set by a generic: if there is a larger
260 // memory (imem/dmem), the value will still be correct
261 int pmemAddressWidth = 0;
262 if (pmemInfo_.asAddrw != 32) {
263 pmemAddressWidth =
264 pmemInfo_.portAddrw +
265 MathTools::requiredBits0Bit0(std::max(
266 0, pmemInfo_.mauWidth * pmemInfo_.widthInMaus / 8 - 1));
267 } else {
268 pmemAddressWidth = DEFAULT_LOCAL_MEMORY_WIDTH;
269 }
270 int axiAddressWidth = std::max(
271 std::max(imemAddressWidth, debugAddressWidth),
272 std::max(dmemAddressWidth, pmemAddressWidth));
273
274 return Conversion::toString(axiAddressWidth + 2);
275}
VHDL_ARRAY
@ VHDL_ARRAY
Definition MemoryGenerator.hh:60
AlmaIFIntegrator::DEFAULT_LOCAL_MEMORY_WIDTH
static const int DEFAULT_LOCAL_MEMORY_WIDTH
Definition AlmaIFIntegrator.hh:123
AlmaIFIntegrator::axiAddressWidth
TCEString axiAddressWidth() const
Definition AlmaIFIntegrator.cc:243
MathTools::requiredBits0Bit0
static int requiredBits0Bit0(long unsigned int number)
PlatformIntegrator::imemInfo
const MemInfo & imemInfo() const
Definition PlatformIntegrator.cc:662

References MemInfo::asAddrw, axiAddressWidth(), DEFAULT_LOCAL_MEMORY_WIDTH, dmemInfo_, PlatformIntegrator::imemInfo(), MemInfo::mauWidth, pmemInfo_, MemInfo::portAddrw, MathTools::requiredBits0Bit0(), Conversion::toString(), VHDL_ARRAY, and MemInfo::widthInMaus.

Referenced by axiAddressWidth(), and initAlmaifBlock().

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◆ axiMasterPortGroup()

NetlistPortGroup * AlmaIFIntegrator::axiMasterPortGroup ( )
private

Builds a representation of the AXI4-Lite master interface as a port group.

Definition at line 763 of file AlmaIFIntegrator.cc.

763 {
764 NetlistPortGroup* axiBus = new NetlistPortGroup(ProGe::SignalGroup());
765
766 addPortToGroup(axiBus, ProGe::OUT, "m_axi_awaddr", "32");
767 addPortToGroup(axiBus, ProGe::OUT, "m_axi_awvalid", "1");
768 addPortToGroup(axiBus, ProGe::IN, "m_axi_awready", "1");
769 addPortToGroup(axiBus, ProGe::OUT, "m_axi_awprot", "3");
770 addPortToGroup(axiBus, ProGe::OUT, "m_axi_wvalid", "1");
771 addPortToGroup(axiBus, ProGe::IN, "m_axi_wready", "1");
772 addPortToGroup(axiBus, ProGe::OUT, "m_axi_wdata", "32");
773 addPortToGroup(axiBus, ProGe::OUT, "m_axi_wstrb", "4");
774 addPortToGroup(axiBus, ProGe::IN, "m_axi_bvalid", "1");
775 addPortToGroup(axiBus, ProGe::OUT, "m_axi_bready", "1");
776 addPortToGroup(axiBus, ProGe::OUT, "m_axi_arvalid", "1");
777 addPortToGroup(axiBus, ProGe::IN, "m_axi_arready", "1");
778 addPortToGroup(axiBus, ProGe::OUT, "m_axi_araddr", "32");
779 addPortToGroup(axiBus, ProGe::OUT, "m_axi_arprot", "3");
780 addPortToGroup(axiBus, ProGe::IN, "m_axi_rdata", "32");
781 addPortToGroup(axiBus, ProGe::IN, "m_axi_rvalid", "1");
782 addPortToGroup(axiBus, ProGe::OUT, "m_axi_rready", "1");
783
784 return axiBus;
785}
AlmaIFIntegrator::addPortToGroup
void addPortToGroup(ProGe::NetlistPortGroup *port_group, const ProGe::Direction dir, const TCEString name, const TCEString width)
Definition AlmaIFIntegrator.cc:708

References addPortToGroup(), ProGe::IN, and ProGe::OUT.

Referenced by initAlmaifBlock().

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◆ axiSlavePortGroup()

NetlistPortGroup * AlmaIFIntegrator::axiSlavePortGroup ( )
private

Builds a representation of the AXI4 bus slave interface as a port group. Hardcoded signal widths for data (32b) and IDs (12b)

Definition at line 724 of file AlmaIFIntegrator.cc.

724 {
725 NetlistPortGroup* axiBus = new NetlistPortGroup(ProGe::SignalGroup());
726
727 addPortToGroup(axiBus, ProGe::IN, "s_axi_awid", "axi_id_width_g");
728 addPortToGroup(axiBus, ProGe::IN, "s_axi_awaddr", "axi_addr_width_g");
729 addPortToGroup(axiBus, ProGe::IN, "s_axi_awlen", "8");
730 addPortToGroup(axiBus, ProGe::IN, "s_axi_awsize", "3");
731 addPortToGroup(axiBus, ProGe::IN, "s_axi_awburst", "2");
732 addPortToGroup(axiBus, ProGe::IN, "s_axi_awvalid", "1");
733 addPortToGroup(axiBus, ProGe::OUT, "s_axi_awready", "1");
734 addPortToGroup(axiBus, ProGe::IN, "s_axi_wdata", "32");
735 addPortToGroup(axiBus, ProGe::IN, "s_axi_wstrb", "4");
736 addPortToGroup(axiBus, ProGe::IN, "s_axi_wvalid", "1");
737 addPortToGroup(axiBus, ProGe::OUT, "s_axi_wready", "1");
738 addPortToGroup(axiBus, ProGe::OUT, "s_axi_bid", "axi_id_width_g");
739 addPortToGroup(axiBus, ProGe::OUT, "s_axi_bresp", "2");
740 addPortToGroup(axiBus, ProGe::OUT, "s_axi_bvalid", "1");
741 addPortToGroup(axiBus, ProGe::IN, "s_axi_bready", "1");
742 addPortToGroup(axiBus, ProGe::IN, "s_axi_arid", "axi_id_width_g");
743 addPortToGroup(axiBus, ProGe::IN, "s_axi_araddr", "axi_addr_width_g");
744 addPortToGroup(axiBus, ProGe::IN, "s_axi_arlen", "8");
745 addPortToGroup(axiBus, ProGe::IN, "s_axi_arsize", "3");
746 addPortToGroup(axiBus, ProGe::IN, "s_axi_arburst", "2");
747 addPortToGroup(axiBus, ProGe::IN, "s_axi_arvalid", "1");
748 addPortToGroup(axiBus, ProGe::OUT, "s_axi_arready", "1");
749 addPortToGroup(axiBus, ProGe::OUT, "s_axi_rid", "axi_id_width_g");
750 addPortToGroup(axiBus, ProGe::OUT, "s_axi_rdata", "32");
751 addPortToGroup(axiBus, ProGe::OUT, "s_axi_rresp", "2");
752 addPortToGroup(axiBus, ProGe::OUT, "s_axi_rlast", "1");
753 addPortToGroup(axiBus, ProGe::OUT, "s_axi_rvalid", "1");
754 addPortToGroup(axiBus, ProGe::IN, "s_axi_rready", "1");
755
756 return axiBus;
757}

References addPortToGroup(), ProGe::IN, and ProGe::OUT.

Referenced by initAlmaifBlock().

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◆ chopTaggedSignals()

bool AlmaIFIntegrator::chopTaggedSignals ( ) const
virtual

Implements PlatformIntegrator.

Definition at line 1124 of file AlmaIFIntegrator.cc.

1124 {
1125 return true;
1126}

◆ connectCoreMemories()

void AlmaIFIntegrator::connectCoreMemories ( MemInfo  mem,
TCEString  mem_name,
TCEString  mem_block_name,
bool  seconds 
)
private

Definition at line 563 of file AlmaIFIntegrator.cc.

564 {
565 almaifBlock_->setParameter(
566 mem_name + "_data_width_g", "integer",
567 Conversion::toString(mem.mauWidth * mem.widthInMaus));
568 almaifBlock_->setParameter(
569 mem_name + "_addr_width_g", "integer",
570 Conversion::toString(mem.portAddrw));
571
572 TCEString platformPath = Environment::dataDirPath("ProGe");
573 platformPath << FileSystem::DIRECTORY_SEPARATOR << "platform"
574 << FileSystem::DIRECTORY_SEPARATOR;
575
576 // If given memory wasn't found by findMemories(), we need dummy signals
577 // as a stand-in for the missing ports
578 if (mem.portAddrw == 0 || mem.type == DRAM) {
579 Path snippet(platformPath + mem_name + "_signal_declaration.snippet");
580 accelInstantiator_.replacePlaceholderFromFile(
581 mem_name + "-signal-declarations", snippet);
582 return;
583 }
584
585 // Otherwise, instantiate the ports
586 if (mem_name == "pmem" && broadcast_pmem_) {
587 Path snippet(platformPath + "pmem_port_declaration_wide.snippet");
588 accelInstantiator_.replacePlaceholderFromFile(
589 mem_name + "-port-declarations", snippet);
590 } else {
591 Path snippet(platformPath + mem_name + "_port_declaration.snippet");
592 accelInstantiator_.replacePlaceholderFromFile(
593 mem_name + "-port-declarations", snippet);
594 }
595
596 TCEString lsu_prefix = "fu_" + mem.lsuName;
597
598 int coreCount = 1;
599 addPortToAlmaIFBlock(
600 "core_" + mem_name + "_avalid_in", coreCount, ProGe::IN,
601 lsu_prefix + "_avalid_out");
602 addPortToAlmaIFBlock(
603 "core_" + mem_name + "_aready_out", coreCount, ProGe::OUT,
604 lsu_prefix + "_aready_in");
605 addPortToAlmaIFBlock(
606 "core_" + mem_name + "_aaddr_in", coreCount * mem.portAddrw,
607 ProGe::IN, lsu_prefix + "_aaddr_out");
608 addPortToAlmaIFBlock(
609 "core_" + mem_name + "_awren_in", coreCount, ProGe::IN,
610 lsu_prefix + "_awren_out");
611 addPortToAlmaIFBlock(
612 "core_" + mem_name + "_astrb_in",
613 (mem.mauWidth * mem.widthInMaus + 7) / 8 * coreCount, ProGe::IN,
614 lsu_prefix + "_astrb_out");
615
616 addPortToAlmaIFBlock(
617 "core_" + mem_name + "_adata_in",
618 coreCount * mem.mauWidth * mem.widthInMaus, ProGe::IN,
619 lsu_prefix + "_adata_out");
620 addPortToAlmaIFBlock(
621 "core_" + mem_name + "_rvalid_out", coreCount, ProGe::OUT,
622 lsu_prefix + "_rvalid_in");
623 addPortToAlmaIFBlock(
624 "core_" + mem_name + "_rready_in", coreCount, ProGe::IN,
625 lsu_prefix + "_rready_out");
626 addPortToAlmaIFBlock(
627 "core_" + mem_name + "_rdata_out",
628 coreCount * mem.mauWidth * mem.widthInMaus, ProGe::OUT,
629 lsu_prefix + "_rdata_in");
630
631 if (seconds) {
632 int addrWidth, dataWidth;
633 if (mem.asName == DMEM_NAME) {
634 addrWidth = secondDmemAddrw_;
635 dataWidth = secondDmemDataw_;
636 lsu_prefix = "fu_" + secondDmemName_;
637 } else {
638 addrWidth = secondPmemAddrw_;
639 dataWidth = secondPmemDataw_;
640 lsu_prefix = "fu_" + secondPmemName_;
641 }
642 addPortToAlmaIFBlock(
643 "core_" + mem_name + "_2nd_avalid_in", coreCount, ProGe::IN,
644 lsu_prefix + "_avalid_out");
645 addPortToAlmaIFBlock(
646 "core_" + mem_name + "_2nd_aready_out", coreCount, ProGe::OUT,
647 lsu_prefix + "_aready_in");
648 addPortToAlmaIFBlock(
649 "core_" + mem_name + "_2nd_aaddr_in", coreCount * addrWidth,
650 ProGe::IN, lsu_prefix + "_aaddr_out");
651 addPortToAlmaIFBlock(
652 "core_" + mem_name + "_2nd_awren_in", coreCount, ProGe::IN,
653 lsu_prefix + "_awren_out");
654 addPortToAlmaIFBlock(
655 "core_" + mem_name + "_2nd_astrb_in", coreCount * dataWidth / 8,
656 ProGe::IN, lsu_prefix + "_astrb_out");
657
658 addPortToAlmaIFBlock(
659 "core_" + mem_name + "_2nd_adata_in", coreCount * dataWidth,
660 ProGe::IN, lsu_prefix + "_adata_out");
661 addPortToAlmaIFBlock(
662 "core_" + mem_name + "_2nd_rvalid_out", coreCount, ProGe::OUT,
663 lsu_prefix + "_rvalid_in");
664 addPortToAlmaIFBlock(
665 "core_" + mem_name + "_2nd_rready_in", coreCount, ProGe::IN,
666 lsu_prefix + "_rready_out");
667 addPortToAlmaIFBlock(
668 "core_" + mem_name + "_2nd_rdata_out", coreCount * dataWidth,
669 ProGe::OUT, lsu_prefix + "_rdata_in");
670 }
671
672 addMemoryPorts(
673 mem_block_name + "_a", mem.mauWidth * mem.widthInMaus, mem.portAddrw,
674 mem.isShared, (mem.asAddrw == 32 && (mem.asName == PMEM_NAME)));
675 if (mem.asName == DMEM_NAME) {
676 addMemoryPorts(
677 mem_block_name + "_b", secondDmemDataw_, secondDmemAddrw_,
678 mem.isShared, false);
679 } else {
680 bool make_local_sized =
681 mem.asAddrw == 32 && (mem.asName == PMEM_NAME);
682 addMemoryPorts(
683 mem_block_name + "_b", secondPmemDataw_, secondPmemAddrw_,
684 mem.isShared, make_local_sized);
685 }
686}
DRAM
@ DRAM
Definition MemoryGenerator.hh:63
AlmaIFIntegrator::secondPmemName_
std::string secondPmemName_
Definition AlmaIFIntegrator.hh:143
AlmaIFIntegrator::DMEM_NAME
static const TCEString DMEM_NAME
Definition AlmaIFIntegrator.hh:116
AlmaIFIntegrator::PMEM_NAME
static const TCEString PMEM_NAME
Definition AlmaIFIntegrator.hh:117
AlmaIFIntegrator::secondDmemName_
std::string secondDmemName_
Definition AlmaIFIntegrator.hh:140
ProGe::NetlistBlock::setParameter
void setParameter(const std::string &name, const std::string &type, const std::string &value)
Definition NetlistBlock.cc:89
MemInfo::type
MemType type
Definition MemoryGenerator.hh:68
MemInfo::lsuName
TCEString lsuName
Definition MemoryGenerator.hh:75
MemInfo::asName
TCEString asName
Definition MemoryGenerator.hh:74

References accelInstantiator_, addMemoryPorts(), addPortToAlmaIFBlock(), almaifBlock_, MemInfo::asAddrw, MemInfo::asName, broadcast_pmem_, Environment::dataDirPath(), FileSystem::DIRECTORY_SEPARATOR, DMEM_NAME, DRAM, ProGe::IN, MemInfo::isShared, MemInfo::lsuName, MemInfo::mauWidth, ProGe::OUT, PMEM_NAME, MemInfo::portAddrw, HDLTemplateInstantiator::replacePlaceholderFromFile(), secondDmemAddrw_, secondDmemDataw_, secondDmemName_, secondPmemAddrw_, secondPmemDataw_, secondPmemName_, ProGe::NetlistBlock::setParameter(), Conversion::toString(), MemInfo::type, and MemInfo::widthInMaus.

Referenced by initAlmaifBlock().

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◆ copyPlatformFile()

void AlmaIFIntegrator::copyPlatformFile ( const TCEString  inputPath,
std::vector< TCEString > &  fileList,
bool  isScript = false 
) const
private

Definition at line 887 of file AlmaIFIntegrator.cc.

889 {
890 TCEString outputPath;
891 if (isScript) {
892 outputPath = progeFilePath(FileSystem::fileOfPath(inputPath), true);
893 } else {
894 outputPath = outputFilePath(FileSystem::fileOfPath(inputPath), true);
895 }
896
897 FileSystem::copy(inputPath, outputPath);
898 fileList.push_back(outputPath);
899}
FileSystem::fileOfPath
static std::string fileOfPath(const std::string pathName)
Definition FileSystem.cc:101
FileSystem::copy
static void copy(const std::string &source, const std::string &target)
Definition FileSystem.cc:524

References FileSystem::copy(), FileSystem::fileOfPath(), PlatformIntegrator::outputFilePath(), PlatformIntegrator::outputPath(), and PlatformIntegrator::progeFilePath().

Referenced by addAlmaifFiles().

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◆ deviceFamily()

TCEString AlmaIFIntegrator::deviceFamily ( ) const
virtual

Returns the FPGA device family

Implements PlatformIntegrator.

Definition at line 1129 of file AlmaIFIntegrator.cc.

1129 {
1130
1131 return deviceFamily_;
1132}

References deviceFamily_.

◆ devicePackage()

TCEString AlmaIFIntegrator::devicePackage ( ) const
virtual

Returns the device package name

Implements PlatformIntegrator.

Definition at line 1142 of file AlmaIFIntegrator.cc.

1142 {
1143 return "";
1144}

◆ deviceSpeedClass()

TCEString AlmaIFIntegrator::deviceSpeedClass ( ) const
virtual

Returns the device speed class

Implements PlatformIntegrator.

Definition at line 1147 of file AlmaIFIntegrator.cc.

1147 {
1148 return "";
1149}

◆ dmemInstance()

MemoryGenerator & AlmaIFIntegrator::dmemInstance ( MemInfo  dmem,
TTAMachine::FunctionUnit &  lsuArch,
std::vector< std::string >  lsuPorts 
)
protectedvirtual

Implements PlatformIntegrator.

Definition at line 1026 of file AlmaIFIntegrator.cc.

1028 {
1029 if (dmem.asName ==
1030 AXI_AS_NAME) { // AXI bus, export all ports to toplevel
1031 return *(new DummyMemGenerator(
1032 dmem.mauWidth, dmem.widthInMaus, dmem.portAddrw, this,
1033 warningStream(), errorStream()));
1034 }
1035
1036 bool genSingleRam = false;
1037 bool genDualPortRam = false;
1038 bool overrideAsWidth = false;
1039 bool isDmem = dmem.asName == DMEM_NAME;
1040 bool isPmem = dmem.asName == PMEM_NAME;
1041 bool isSecondInstance = false;
1042
1043 if (dmem.type == DRAM) { // AXI bus, export all ports to toplevel
1044 return *(new DummyMemGenerator(
1045 dmem.mauWidth, dmem.widthInMaus, dmem.portAddrw, this,
1046 warningStream(), errorStream()));
1047 }
1048
1049 int bDataWidth = 0;
1050 int bAddrWidth = 0;
1051
1052 if (isDmem || isPmem) {
1053 genDualPortRam = true;
1054 genSingleRam = dmem.isShared;
1055 if (isDmem) {
1056 if (dmemHandled_) {
1057 isSecondInstance = true;
1058 }
1059 dmem = dmemInfo_;
1060 bDataWidth = secondDmemDataw_;
1061 bAddrWidth = secondDmemAddrw_;
1062 dmemHandled_ = true;
1063 }
1064 if (isPmem) {
1065 if (pmemHandled_) {
1066 isSecondInstance = true;
1067 }
1068 dmem = pmemInfo_;
1069 bDataWidth = secondPmemDataw_;
1070 bAddrWidth = secondPmemAddrw_;
1071 pmemHandled_ = true;
1072 }
1073
1074 // TODO: Assumes 32b wide memory (32b address - 2 mask bits)
1075 // (the AXI-lite IF also assumes this)
1076 if (dmem.asName == PMEM_NAME && dmem.asAddrw == 32) {
1077 overrideAsWidth = true;
1078 }
1079 }
1080
1081 MemoryGenerator* memGen = NULL;
1082
1083 if ((isSecondInstance && dmem.isShared) || dmem.type == DRAM) {
1084 memGen = new DummyMemGenerator(
1085 dmem.mauWidth, dmem.widthInMaus, dmem.portAddrw, this,
1086 warningStream(), errorStream());
1087 } else if (dmemGen_.find(dmem.asName) != dmemGen_.end()) {
1088 memGen = dmemGen_.find(dmem.asName)->second;
1089 } else {
1090 if (dmem.type == ONCHIP) {
1091 // onchip mem size is scalable, use value from adf's Address Space
1092 int addrw = dmem.portAddrw;
1093 memGen = new XilinxBlockRamGenerator(
1094 dmem.mauWidth, dmem.widthInMaus, addrw, bDataWidth,
1095 bAddrWidth, this, warningStream(), errorStream(),
1096 genDualPortRam, almaifBlock_, dmem.asName, overrideAsWidth,
1097 genSingleRam);
1098 } else {
1099 TCEString msg = "Unsupported data memory type";
1100 throw InvalidData(__FILE__, __LINE__, "AlmaIFIntegrator", msg);
1101 }
1102 memGen->addLsu(lsuArch, lsuPorts);
1103 dmemGen_[dmem.asName] = memGen;
1104 }
1105 return *memGen;
1106}
ONCHIP
@ ONCHIP
Definition MemoryGenerator.hh:61
AlmaIFIntegrator::AXI_AS_NAME
static const TCEString AXI_AS_NAME
Definition AlmaIFIntegrator.hh:118
MemoryGenerator::addLsu
void addLsu(TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
Definition MemoryGenerator.cc:376

References MemoryGenerator::addLsu(), almaifBlock_, MemInfo::asAddrw, MemInfo::asName, AXI_AS_NAME, DMEM_NAME, dmemGen_, dmemHandled_, dmemInfo_, DRAM, PlatformIntegrator::errorStream(), MemInfo::isShared, MemInfo::mauWidth, ONCHIP, PMEM_NAME, pmemHandled_, pmemInfo_, MemInfo::portAddrw, secondDmemAddrw_, secondDmemDataw_, secondPmemAddrw_, secondPmemDataw_, MemInfo::type, PlatformIntegrator::warningStream(), and MemInfo::widthInMaus.

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◆ exportUnconnectedPorts()

void AlmaIFIntegrator::exportUnconnectedPorts ( int  coreId)
privatevirtual

Reimplemented from PlatformIntegrator.

Definition at line 979 of file AlmaIFIntegrator.cc.

979 {
980 PlatformIntegrator::exportUnconnectedPorts(coreId);
981
982 for (size_t i = 0; i < almaifBlock_->portCount(); i++) {
983 const NetlistPort& port = almaifBlock_->port(i);
984 if (!integratorBlock()->netlist().isPortConnected(port)) {
985 connectToplevelPort(port);
986 }
987 }
988}
PlatformIntegrator::exportUnconnectedPorts
virtual void exportUnconnectedPorts(int coreId)
Definition PlatformIntegrator.cc:464
PlatformIntegrator::connectToplevelPort
virtual void connectToplevelPort(const ProGe::NetlistPort &corePort, const TCEString signalPrefix="")
Definition PlatformIntegrator.cc:475
PlatformIntegrator::integratorBlock
ProGe::NetlistBlock * integratorBlock()
Definition PlatformIntegrator.cc:302
ProGe::NetlistBlock::port
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
Definition NetlistBlock.cc:97
ProGe::NetlistBlock::portCount
virtual size_t portCount() const
Definition BaseNetlistBlock.cc:248

References almaifBlock_, PlatformIntegrator::connectToplevelPort(), PlatformIntegrator::exportUnconnectedPorts(), PlatformIntegrator::integratorBlock(), ProGe::NetlistBlock::port(), and ProGe::NetlistBlock::portCount().

Referenced by integrateCore().

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◆ findMemories()

void AlmaIFIntegrator::findMemories ( )
private

Definition at line 114 of file AlmaIFIntegrator.cc.

114 {
115 dmemInfo_ = pmemInfo_ = {UNKNOWN, 0, 0, 0, 0, false, "", ""};
116
117 bool foundDmem = false;
118 bool foundPmem = false;
119
120 // This is more or less a duplicate of parseDataMemories in the superclass
121 // to get around it not parsing memories if dmem type is 'none' and it not
122 // handling multiple lsus well
123
124 MemInfo secondDmemInfo;
125 MemInfo secondPmemInfo;
126 TTAMachine::Machine::FunctionUnitNavigator fuNav =
127 this->machine()->functionUnitNavigator();
128 for (int i = 0; i < fuNav.count(); i++) {
129 TTAMachine::FunctionUnit* fu = fuNav.item(i);
130 if (fu->hasAddressSpace()) {
131 TTAMachine::AddressSpace* as = fu->addressSpace();
132 bool isLSU = false;
133 for (int i = 0; i < fu->operationCount(); ++i) {
134 std::string operation = fu->operation(i)->name();
135 std::string prefix = operation.substr(0, 2);
136 if (prefix == "ld" || prefix == "st") {
137 isLSU = true;
138 break;
139 }
140 }
141
142 if (!isLSU) {
143 continue;
144 }
145
146 if (as->name() == DMEM_NAME) {
147 if (foundDmem) {
148 assert(!secondDmem_ && "Found third DMEM LSU");
149 secondDmem_ = true;
150 secondDmemInfo = readLsuParameters(*fu);
151 if (secondDmemInfo.portAddrw < dmemInfo_.portAddrw) {
152 // Second DMEM should have lesser or equal data
153 // width => greater or equal address width
154 // swap if this is not the case
155 secondDmemInfo = dmemInfo_;
156 dmemInfo_ = readLsuParameters(*fu);
157 }
158 secondDmemName_ = secondDmemInfo.lsuName;
159 } else {
160 foundDmem = true;
161 dmemInfo_ = readLsuParameters(*fu);
162 if (dmem_dram_) {
163 dmemInfo_.type = DRAM;
164 }
165 }
166 } else if (as->name() == PMEM_NAME) {
167 if (foundPmem) {
168 assert(!secondPmem_ && "Found third PMEM LSU");
169 secondPmem_ = true;
170 secondPmemInfo = readLsuParameters(*fu);
171 } else {
172 foundPmem = true;
173 pmemInfo_ = readLsuParameters(*fu);
174
175 // Needed for the case when the local memory doesn't exist
176 // and needs to reserved from the buffer memory
177 if (as->hasNumericalId(0)) {
178 hasSeparateLocalMemory_ = false;
179 }
180 }
181 }
182 }
183 }
184
185 if (secondDmem_) {
186 secondDmemName_ = secondDmemInfo.lsuName;
187 secondDmemDataw_ =
188 secondDmemInfo.mauWidth * secondDmemInfo.widthInMaus;
189 secondDmemAddrw_ = secondDmemInfo.portAddrw;
190 } else if (foundDmem) {
191 secondDmemDataw_ = 32;
192 secondDmemAddrw_ = dmemInfo_.asAddrw - 2;
193 }
194
195 if (secondPmem_) {
196 secondPmemName_ = secondPmemInfo.lsuName;
197 secondPmemDataw_ =
198 secondPmemInfo.mauWidth * secondDmemInfo.widthInMaus;
199 secondPmemAddrw_ = secondPmemInfo.portAddrw;
200 } else if (foundPmem) {
201 secondPmemDataw_ = 32;
202 secondPmemAddrw_ = pmemInfo_.asAddrw - 2;
203 }
204}
assert
#define assert(condition)
Definition Application.hh:86
UNKNOWN
@ UNKNOWN
Definition MemoryGenerator.hh:58
PlatformIntegrator::readLsuParameters
MemInfo readLsuParameters(const TTAMachine::FunctionUnit &lsu)
Definition PlatformIntegrator.cc:414
TTAMachine::AddressSpace::hasNumericalId
virtual bool hasNumericalId(unsigned id) const
Definition AddressSpace.cc:383
TTAMachine::Component::name
virtual TCEString name() const
Definition MachinePart.cc:125
TTAMachine::FunctionUnit::addressSpace
virtual AddressSpace * addressSpace() const
Definition FunctionUnit.cc:580
TTAMachine::FunctionUnit::operation
virtual HWOperation * operation(const std::string &name) const
Definition FunctionUnit.cc:363
TTAMachine::FunctionUnit::operationCount
virtual int operationCount() const
Definition FunctionUnit.cc:419
TTAMachine::FunctionUnit::hasAddressSpace
virtual bool hasAddressSpace() const
Definition FunctionUnit.cc:608
TTAMachine::HWOperation::name
const std::string & name() const
Definition HWOperation.cc:141
TTAMachine::Machine::Navigator::item
ComponentType * item(int index) const
TTAMachine::Machine::functionUnitNavigator
virtual FunctionUnitNavigator functionUnitNavigator() const
Definition Machine.cc:380

References TTAMachine::FunctionUnit::addressSpace(), MemInfo::asAddrw, assert, TTAMachine::Machine::Navigator< ComponentType >::count(), dmem_dram_, DMEM_NAME, dmemInfo_, DRAM, TTAMachine::Machine::functionUnitNavigator(), TTAMachine::FunctionUnit::hasAddressSpace(), TTAMachine::AddressSpace::hasNumericalId(), hasSeparateLocalMemory_, TTAMachine::Machine::Navigator< ComponentType >::item(), MemInfo::lsuName, PlatformIntegrator::machine(), MemInfo::mauWidth, TTAMachine::HWOperation::name(), TTAMachine::Component::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), PMEM_NAME, pmemInfo_, MemInfo::portAddrw, PlatformIntegrator::readLsuParameters(), secondDmem_, secondDmemAddrw_, secondDmemDataw_, secondDmemName_, secondPmem_, secondPmemAddrw_, secondPmemDataw_, secondPmemName_, MemInfo::type, UNKNOWN, and MemInfo::widthInMaus.

Referenced by integrateProcessor().

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◆ generateIntegratedTestbench()

void AlmaIFIntegrator::generateIntegratedTestbench ( )
private

Definition at line 1167 of file AlmaIFIntegrator.cc.

1167 {
1168 const TCEString DS = FileSystem::DIRECTORY_SEPARATOR;
1169
1170 FileSystem::createDirectory(progeFilePath("tb", true));
1171
1172 TCEString basePath = Environment::dataDirPath("ProGe");
1173 TCEString tbPath = basePath + DS + "tb" + DS + "almaif" + DS;
1174 TCEString outputPath = tbFilePath("almaif-tb.vhdl", true);
1175
1176 HDLTemplateInstantiator tbInstantiator(coreEntityName());
1177 if (pmemInfo_.asAddrw == 32) {
1178 tbInstantiator.replacePlaceholderFromFile(
1179 "m-axi-port-declarations",
1180 Path(tbPath + "almaif-tb-m-axi-port-declarations-snippet.vhdl"));
1181 tbInstantiator.replacePlaceholderFromFile(
1182 "m-axi-port-connections",
1183 Path(tbPath + "almaif-tb-m-axi-port-connections-snippet.vhdl"));
1184 tbInstantiator.replacePlaceholderFromFile(
1185 "m-axi-external-mem-instantiation",
1186 Path(
1187 tbPath +
1188 "almaif-tb-m-axi-external-mem-instantiation-snippet.vhdl"));
1189 FileSystem::copy(tbPath + "axi-mem.vhdl", tbFilePath("axi-mem.vhdl"));
1190 }
1191 tbInstantiator.instantiateTemplateFile(
1192 tbPath + "almaif-tb.vhdl.tmpl", outputPath);
1193}
FileSystem::createDirectory
static bool createDirectory(const std::string &path)
Definition FileSystem.cc:400
PlatformIntegrator::tbFilePath
TCEString tbFilePath(TCEString fileName, bool absolute=false) const
Definition PlatformIntegrator.cc:168

References MemInfo::asAddrw, FileSystem::copy(), PlatformIntegrator::coreEntityName(), FileSystem::createDirectory(), Environment::dataDirPath(), FileSystem::DIRECTORY_SEPARATOR, DS, HDLTemplateInstantiator::instantiateTemplateFile(), PlatformIntegrator::outputPath(), pmemInfo_, PlatformIntegrator::progeFilePath(), HDLTemplateInstantiator::replacePlaceholderFromFile(), and PlatformIntegrator::tbFilePath().

Referenced by integrateProcessor().

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◆ imemInstance()

MemoryGenerator & AlmaIFIntegrator::imemInstance ( MemInfo  imem,
int  coreId 
)
protectedvirtual

Implements PlatformIntegrator.

Definition at line 991 of file AlmaIFIntegrator.cc.

991 {
992 assert(imem.type != UNKNOWN && "Imem type not set!");
993 int axiAddrWidth =
994 MathTools::requiredBits0Bit0(
995 (imemInfo().widthInMaus * imemInfo().mauWidth + 31) / 32 - 1) +
996 imemInfo().portAddrw;
997 if (imemGen_ == NULL) {
998 if (imem.type == ONCHIP) {
999 if (imem_dp_) {
1000 imemGen_ = new XilinxBlockRamGenerator(
1001 MathTools::roundUpToPowerTwo(imem.mauWidth),
1002 imem.widthInMaus, imem.portAddrw,
1003 MathTools::roundUpToPowerTwo(imem.mauWidth),
1004 imem.portAddrw, this, warningStream(), errorStream(),
1005 true, almaifBlock_, "INSTR", false, false);
1006 } else {
1007 imemGen_ = new XilinxBlockRamGenerator(
1008 imem.mauWidth, imem.widthInMaus, imem.portAddrw, 32,
1009 axiAddrWidth, this, warningStream(), errorStream(), true,
1010 almaifBlock_, "INSTR", false, false);
1011 }
1012 } else if (imem.type == VHDL_ARRAY) {
1013 imemGen_ = new VhdlRomGenerator(
1014 imem.mauWidth, imem.widthInMaus, imem.portAddrw,
1015 programName() + "_imem_pkg.vhdl", this, warningStream(),
1016 errorStream());
1017 } else if (imem.type != NONE) {
1018 TCEString msg = "Unsupported instruction memory type";
1019 throw InvalidData(__FILE__, __LINE__, "AlmaIFIntegrator", msg);
1020 }
1021 }
1022 return *imemGen_;
1023}
NONE
@ NONE
Definition MemoryGenerator.hh:59
MathTools::roundUpToPowerTwo
static unsigned int roundUpToPowerTwo(unsigned int number)

References almaifBlock_, assert, PlatformIntegrator::errorStream(), imem_dp_, imemGen_, PlatformIntegrator::imemInfo(), MemInfo::mauWidth, NONE, ONCHIP, MemInfo::portAddrw, PlatformIntegrator::programName(), MathTools::requiredBits0Bit0(), MathTools::roundUpToPowerTwo(), MemInfo::type, UNKNOWN, VHDL_ARRAY, PlatformIntegrator::warningStream(), and MemInfo::widthInMaus.

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◆ initAlmaifBlock()

void AlmaIFIntegrator::initAlmaifBlock ( )
private

Definition at line 278 of file AlmaIFIntegrator.cc.

278 {
279 ProGe::Netlist& netlist = integratorBlock()->netlist();
280 TCEString core_count = "1";
281
282 TCEString platformPath = Environment::dataDirPath("ProGe");
283 platformPath << FileSystem::DIRECTORY_SEPARATOR << "platform"
284 << FileSystem::DIRECTORY_SEPARATOR;
285
286 int imemdataw = imemInfo().mauWidth * imemInfo().widthInMaus;
287 int imemaddrw = imemInfo().portAddrw;
288 int imemAxiAddrw =
289 MathTools::requiredBits0Bit0((imemdataw + 31) / 32 - 1) + imemaddrw;
290 int bustrace_width = 0;
291
292 if (imem_dp_) {
293 imemdataw = MathTools::roundUpToPowerTwo(imemdataw);
294 }
295
296 for (int i = 0; i < machine()->busNavigator().count(); ++i) {
297 int bus_width = machine()->busNavigator().item(i)->width();
298 // Busess are padded to a multiple of 32 bits
299 bus_width = (bus_width + 31) / 32 * 32;
300 bustrace_width += bus_width;
301 }
302
303 almaifBlock_ = new NetlistBlock(
304 ALMAIF_MODULE, ALMAIF_MODULE + "_0", integratorBlock());
305
306 netlist.setParameter("AXI_ADDR_WIDTH", "integer", axiAddressWidth());
307 integratorBlock()->setParameter(
308 "axi_addr_width_g", "integer", "AXI_ADDR_WIDTH");
309 netlist.setParameter("AXI_ID_WIDTH", "integer", "12");
310 integratorBlock()->setParameter(
311 "axi_id_width_g", "integer", "AXI_ID_WIDTH");
312 almaifBlock_->setParameter("core_count_g", "integer", core_count);
313 almaifBlock_->setParameter(
314 "axi_addr_width_g", "integer", "axi_addr_width_g");
315 almaifBlock_->setParameter("axi_id_width_g", "integer", "axi_id_width_g");
316
317 almaifBlock_->setParameter(
318 "imem_addr_width_g", "integer", Conversion::toString(imemaddrw));
319
320 almaifBlock_->setParameter(
321 "imem_axi_addr_width_g", "integer",
322 Conversion::toString(imemAxiAddrw));
323 if (imemInfo().type != VHDL_ARRAY) {
324 almaifBlock_->setParameter(
325 "imem_data_width_g", "integer", Conversion::toString(imemdataw));
326 } else {
327 almaifBlock_->setParameter("imem_data_width_g", "integer", "0");
328 }
329
330 almaifBlock_->setParameter(
331 "bus_count_g", "integer", Conversion::toString(bustrace_width / 32));
332 almaifBlock_->setParameter(
333 "local_mem_addrw_g", "integer", "local_mem_addrw_g");
334
335 // Add and connect clock and reset ports
336 NetlistPort* clk =
337 new NetlistPort("clk", "1", 1, ProGe::BIT, ProGe::IN, *almaifBlock_);
338 NetlistPort* rstx =
339 new NetlistPort("rstx", "1", 1, ProGe::BIT, ProGe::IN, *almaifBlock_);
340 netlist.connect(*clockPort(), *clk);
341 netlist.connect(*resetPort(), *rstx);
342
343 almaifBlock_->setParameter(
344 "second_dmem_data_width_g", "integer",
345 Conversion::toString(secondDmemDataw_));
346 almaifBlock_->setParameter(
347 "second_dmem_addr_width_g", "integer",
348 Conversion::toString(secondDmemAddrw_));
349
350 if (secondDmem_) {
351 almaifBlock_->setParameter("enable_second_dmem_g", "integer", "1");
352 accelInstantiator_.replacePlaceholderFromFile(
353 "second-dmem-port-declarations",
354 Path(platformPath + "second_dmem_port_declaration.snippet"));
355 } else {
356 almaifBlock_->setParameter("enable_second_dmem_g", "integer", "0");
357 accelInstantiator_.replacePlaceholderFromFile(
358 "second-dmem-signal-declarations",
359 Path(platformPath + "second_dmem_signal_declaration.snippet"));
360 }
361
362 if (secondPmem_) {
363 almaifBlock_->setParameter("enable_second_pmem_g", "integer", "1");
364 accelInstantiator_.replacePlaceholderFromFile(
365 "second-pmem-port-declarations",
366 Path(platformPath + "second_pmem_port_declaration.snippet"));
367 } else {
368 almaifBlock_->setParameter("enable_second_pmem_g", "integer", "0");
369 accelInstantiator_.replacePlaceholderFromFile(
370 "second-pmem-signal-declarations",
371 Path(platformPath + "second_pmem_signal_declaration.snippet"));
372 }
373
374 almaifBlock_->setParameter(
375 "second_pmem_data_width_g", "integer",
376 Conversion::toString(secondPmemDataw_));
377 if (pmemInfo_.asAddrw == 32) {
378 almaifBlock_->setParameter(
379 "second_pmem_addr_width_g", "integer", "local_mem_addrw_g");
380 } else {
381 almaifBlock_->setParameter(
382 "second_pmem_addr_width_g", "integer",
383 Conversion::toString(secondPmemAddrw_));
384 }
385
386 if (syncReset_) {
387 almaifBlock_->setParameter("sync_reset_g", "integer", "1");
388 } else {
389 almaifBlock_->setParameter("sync_reset_g", "integer", "0");
390 }
391
392 if (broadcast_pmem_) {
393 almaifBlock_->setParameter("broadcast_pmem_g", "integer", "1");
394
395 accelInstantiator_.replacePlaceholderFromFile(
396 "pmem-bcast", Path(platformPath + "pmem_broadcast.snippet"));
397 } else {
398 almaifBlock_->setParameter("broadcast_pmem_g", "integer", "0");
399 }
400
401 // Add AXI4 slave interface to AlmaIF block and toplevel, and connect them
402 NetlistPortGroup* axislave_almaif = axiSlavePortGroup();
403 NetlistPortGroup* axislave_ext = axislave_almaif->clone();
404 almaifBlock_->addPortGroup(axislave_almaif);
405 integratorBlock()->addPortGroup(axislave_ext);
406 netlist.connectGroupByName(*axislave_almaif, *axislave_ext);
407
408 if (pmemInfo_.asAddrw == 32) {
409 assert(
410 broadcast_pmem_ == false &&
411 "Broadcasting pmem not supported with m_axi");
412 integratorBlock()->setParameter(
413 "local_mem_addrw_g", "integer",
414 Conversion::toString(DEFAULT_LOCAL_MEMORY_WIDTH - 2));
415
416 integratorBlock()->setParameter(
417 "axi_offset_low_g", "integer", "1073741824");
418 integratorBlock()->setParameter("axi_offset_high_g", "integer", "0");
419 almaifBlock_->setParameter(
420 "axi_offset_low_g", "integer", "axi_offset_low_g");
421 almaifBlock_->setParameter(
422 "axi_offset_high_g", "integer", "axi_offset_high_g");
423
424 NetlistPortGroup* aximaster_almaif = axiMasterPortGroup();
425 NetlistPortGroup* aximaster_ext = aximaster_almaif->clone();
426 almaifBlock_->addPortGroup(aximaster_almaif);
427 integratorBlock()->addPortGroup(aximaster_ext);
428 netlist.connectGroupByName(*aximaster_almaif, *aximaster_ext);
429 } else {
430 integratorBlock()->setParameter(
431 "local_mem_addrw_g", "integer",
432 Conversion::toString(pmemInfo_.portAddrw));
433 almaifBlock_->setParameter("axi_offset_low_g", "integer", "0");
434 almaifBlock_->setParameter(
435 "axi_offset_high_g", "integer", "0");
436 }
437
438 int coreCount = 1;
439 // Debug signals
440 if (!hasMinimalDebugger_) {
441 almaifBlock_->setParameter("full_debugger_g", "integer", "1");
442 accelInstantiator_.replacePlaceholderFromFile(
443 "full-debugger-port-declarations",
444 Path(platformPath + "full_debugger_port_declaration.snippet"));
445 accelInstantiator_.replacePlaceholderFromFile(
446 "debugger", Path(platformPath + "full_debugger.snippet"));
447
448 addPortToAlmaIFBlock(
449 "core_db_pc_start", coreCount * imemaddrw, ProGe::OUT,
450 "db_pc_start");
451 addPortToAlmaIFBlock(
452 "core_db_pc_next", coreCount * imemaddrw, ProGe::IN,
453 "db_pc_next");
454 addPortToAlmaIFBlock(
455 "core_db_bustraces", coreCount * bustrace_width, ProGe::IN,
456 "db_bustraces");
457 } else {
458 almaifBlock_->setParameter("full_debugger_g", "integer", "0");
459 accelInstantiator_.replacePlaceholderFromFile(
460 "mini-debugger-signal-declarations",
461 Path(platformPath + "mini_debugger_signal_declaration.snippet"));
462 accelInstantiator_.replacePlaceholderFromFile(
463 "debugger", Path(platformPath + "mini_debugger.snippet"));
464 }
465
466 // Set the default value in case when there is no separate scratchpad memory.
467 // AlmaIF interface must reserve some part of the global buffer memory
468 // (pmem) and communicate that in the interface
469 if (!hasSeparateLocalMemory_) {
470 almaifBlock_->setParameter(
471 "reserved_sp_bytes_g", "integer",
472 Conversion::toString(DEFAULT_RESERVED_PRIVATE_MEM_SIZE));
473 }
474
475 addPortToAlmaIFBlock(
476 "core_db_pc", coreCount * imemaddrw, ProGe::IN, "db_pc");
477 addPortToAlmaIFBlock(
478 "core_db_lockcnt", coreCount * 64, ProGe::IN, "db_lockcnt");
479 addPortToAlmaIFBlock(
480 "core_db_cyclecnt", coreCount * 64, ProGe::IN, "db_cyclecnt");
481 addPortToAlmaIFBlock(
482 "core_db_tta_nreset", coreCount, ProGe::OUT, "db_tta_nreset");
483 addPortToAlmaIFBlock(
484 "core_db_lockrq", coreCount, ProGe::OUT, "db_lockrq");
485 if (dmem_dram_) {
486 addPortToAlmaIFBlock(
487 "core_db_dram_offset", 32, ProGe::OUT, "db_dram_offset");
488 accelInstantiator_.replacePlaceholder(
489 "dram-offset-port-declaration",
490 "core_db_dram_offset : out std_logic_vector(32-1 downto 0);");
491 // We want to disable dmem from tta-accel, because dmem exists in dram
492 accelInstantiator_.replacePlaceholder(
493 "enable-dmem", "constant enable_dmem : boolean := false;");
494 } else {
495 // Dummy signal to connect to not leave minidebuggers portmap
496 // undefined
497 accelInstantiator_.replacePlaceholder(
498 "dram-offset-dummy-declaration",
499 "signal core_db_dram_offset : std_logic_vector(32-1 downto 0);");
500 accelInstantiator_.replacePlaceholder(
501 "enable-dmem",
502 "constant enable_dmem : boolean := dmem_data_width_g > 0;");
503 }
504
505 if (imemInfo().type != VHDL_ARRAY) {
506 // Ifetch signals
507 addPortToAlmaIFBlock("core_busy_out", coreCount, ProGe::OUT, "busy");
508 addPortToAlmaIFBlock(
509 "core_imem_data_out", coreCount * imemdataw, ProGe::OUT,
510 "imem_data");
511 addPortToAlmaIFBlock(
512 "core_imem_en_x_in", coreCount, ProGe::IN, "imem_en_x");
513 addPortToAlmaIFBlock(
514 "core_imem_addr_in", coreCount * imemaddrw, ProGe::IN,
515 "imem_addr");
516
517 if (imem_dp_) {
518 const int strb_width = imemdataw / 8;
519 const int half_cores_ceil = (coreCount + 1) / 2;
520 // Dualport memories have identical a-b ports, except with odd
521 // corecounts the b is full and the a's msb-side is unconnected
522 addMemoryPorts(
523 "INSTR_a", half_cores_ceil, imemdataw * half_cores_ceil,
524 imemaddrw * half_cores_ceil, strb_width * half_cores_ceil,
525 false);
526 addMemoryPorts(
527 "INSTR_b", half_cores_ceil, imemdataw * half_cores_ceil,
528 imemaddrw * half_cores_ceil, strb_width * half_cores_ceil,
529 false);
530 } else {
531 addMemoryPorts("INSTR_a", imemdataw, imemaddrw, false, false);
532 addMemoryPorts("INSTR_b", 32, imemAxiAddrw, false, false);
533 }
534 TCEString platformPath = Environment::dataDirPath("ProGe");
535 platformPath << FileSystem::DIRECTORY_SEPARATOR << "platform"
536 << FileSystem::DIRECTORY_SEPARATOR;
537
538 accelInstantiator_.replacePlaceholderFromFile(
539 "imem-statements",
540 Path(platformPath + "imem_statements.snippet"));
541 if (imem_dp_) {
542 accelInstantiator_.replacePlaceholderFromFile(
543 "imem-bcast",
544 Path(platformPath + "imem_broadcast_dualport.snippet"));
545 accelInstantiator_.replacePlaceholderFromFile(
546 "imem-port-declarations",
547 Path(
548 platformPath + "imem_port_declaration_dualport.snippet"));
549 } else {
550 accelInstantiator_.replacePlaceholderFromFile(
551 "imem-bcast", Path(platformPath + "imem_broadcast.snippet"));
552 accelInstantiator_.replacePlaceholderFromFile(
553 "imem-port-declarations",
554 Path(platformPath + "imem_port_declaration.snippet"));
555 }
556 }
557
558 connectCoreMemories(dmemInfo_, "dmem", "data", secondDmem_);
559 connectCoreMemories(pmemInfo_, "pmem", "param", secondPmem_);
560}
AlmaIFIntegrator::axiMasterPortGroup
ProGe::NetlistPortGroup * axiMasterPortGroup()
Definition AlmaIFIntegrator.cc:763
AlmaIFIntegrator::axiSlavePortGroup
ProGe::NetlistPortGroup * axiSlavePortGroup()
Definition AlmaIFIntegrator.cc:724
AlmaIFIntegrator::DEFAULT_RESERVED_PRIVATE_MEM_SIZE
static const int DEFAULT_RESERVED_PRIVATE_MEM_SIZE
Definition AlmaIFIntegrator.hh:122
AlmaIFIntegrator::ALMAIF_MODULE
static const TCEString ALMAIF_MODULE
Definition AlmaIFIntegrator.hh:119
AlmaIFIntegrator::connectCoreMemories
void connectCoreMemories(MemInfo mem, TCEString mem_name, TCEString mem_block_name, bool seconds)
Definition AlmaIFIntegrator.cc:563
PlatformIntegrator::resetPort
ProGe::NetlistPort * resetPort() const
Definition PlatformIntegrator.cc:715
PlatformIntegrator::clockPort
ProGe::NetlistPort * clockPort() const
Definition PlatformIntegrator.cc:703
ProGe::NetlistBlock::addPortGroup
void addPortGroup(NetlistPortGroup *portGroup)
Definition BaseNetlistBlock.cc:508
ProGe::NetlistBlock::netlist
virtual const Netlist & netlist() const
Definition BaseNetlistBlock.cc:348
ProGe::NetlistPortGroup::clone
virtual NetlistPortGroup * clone(bool asMirrored=false) const
Definition NetlistPortGroup.cc:169
ProGe::Netlist::connect
bool connect(const NetlistPort &port1, const NetlistPort &port2, int port1FirstBit, int port2FirstBit, int width=1)
Definition Netlist.cc:83
ProGe::Netlist::setParameter
void setParameter(const std::string &name, const std::string &type, const std::string &value)
Definition Netlist.cc:362
ProGe::Netlist::connectGroupByName
bool connectGroupByName(const NetlistPortGroup &group1, const NetlistPortGroup &group2)
Definition Netlist.cc:238
TTAMachine::Machine::busNavigator
virtual BusNavigator busNavigator() const
Definition Machine.cc:356

References accelInstantiator_, addMemoryPorts(), ProGe::NetlistBlock::addPortGroup(), addPortToAlmaIFBlock(), ALMAIF_MODULE, almaifBlock_, MemInfo::asAddrw, assert, axiAddressWidth(), axiMasterPortGroup(), axiSlavePortGroup(), ProGe::BIT, broadcast_pmem_, TTAMachine::Machine::busNavigator(), PlatformIntegrator::clockPort(), ProGe::NetlistPortGroup::clone(), ProGe::Netlist::connect(), connectCoreMemories(), ProGe::Netlist::connectGroupByName(), TTAMachine::Machine::Navigator< ComponentType >::count(), Environment::dataDirPath(), DEFAULT_LOCAL_MEMORY_WIDTH, DEFAULT_RESERVED_PRIVATE_MEM_SIZE, FileSystem::DIRECTORY_SEPARATOR, dmem_dram_, dmemInfo_, hasMinimalDebugger_, hasSeparateLocalMemory_, imem_dp_, PlatformIntegrator::imemInfo(), ProGe::IN, PlatformIntegrator::integratorBlock(), TTAMachine::Machine::Navigator< ComponentType >::item(), PlatformIntegrator::machine(), MemInfo::mauWidth, ProGe::NetlistBlock::netlist(), ProGe::OUT, pmemInfo_, MemInfo::portAddrw, HDLTemplateInstantiator::replacePlaceholder(), HDLTemplateInstantiator::replacePlaceholderFromFile(), MathTools::requiredBits0Bit0(), PlatformIntegrator::resetPort(), MathTools::roundUpToPowerTwo(), secondDmem_, secondDmemAddrw_, secondDmemDataw_, secondPmem_, secondPmemAddrw_, secondPmemDataw_, ProGe::Netlist::setParameter(), ProGe::NetlistBlock::setParameter(), syncReset_, Conversion::toString(), VHDL_ARRAY, and MemInfo::widthInMaus.

Referenced by integrateProcessor().

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◆ integrateCore()

bool AlmaIFIntegrator::integrateCore ( const ProGe::NetlistBlock &  cores,
int  coreId 
)
virtual

Integrates a single TTA core

Parameters
coresNetlistBlock containing the core(s)
coreIdIndex of the core to be integrated

Reimplemented from PlatformIntegrator.

Definition at line 902 of file AlmaIFIntegrator.cc.

902 {
903 ProGe::Netlist& netlist = integratorBlock()->netlist();
904
905 TCEString clkPortName = PlatformIntegrator::TTA_CORE_CLK;
906 TCEString resetPortName = PlatformIntegrator::TTA_CORE_RSTX;
907
908 if (!createMemories(coreId)) {
909 return false;
910 }
911
912 // Connect cycle count, stall count ports if needed by an FU
913 auto ttaCCPort = core.port("debug_cycle_count_in");
914 if (ttaCCPort) {
915 netlist.connect(*core.port("db_cyclecnt"), *ttaCCPort);
916 }
917 auto ttaLCPort = core.port("debug_lock_count_in");
918 if (ttaLCPort) {
919 netlist.connect(*core.port("db_lockcnt"), *ttaLCPort);
920 }
921 for (size_t i = 0; i < core.portCount(); ++i) {
922 TCEString portName = core.port(i).name();
923
924 // Connect global clock and reset ports
925 if (portName == PlatformIntegrator::TTA_CORE_CLK) {
926 netlist.connect(*clockPort(), core.port(i));
927 } else if (portName == PlatformIntegrator::TTA_CORE_RSTX) {
928 netlist.connect(*resetPort(), core.port(i));
929 } else {
930 // Strip coreN_ -prefix for multicore TTAs
931 if (portName.substr(0, 4) == "core") {
932 TCEString coreKey;
933 coreKey << "core" << coreId;
934 size_t cutoff = portName.find_first_of('_');
935 if (portName.substr(0, cutoff) != coreKey) {
936 // Port doesn't belong to core, skip
937 continue;
938 }
939 portName = portName.substr(cutoff + 1);
940 }
941 if (almaif_ttacore_ports.find(portName) !=
942 almaif_ttacore_ports.end()) {
943 int portWidth = almaif_ttacore_ports[portName]->realWidth();
944
945 // Connect AlmaIF block to TTA
946
947 if (coreId != -1 && imem_dp_ && portName == "imem_data") {
948 // imem_dp_ works with padded imem data signals. So here
949 // we connect only the real bits, but with padded
950 // differences.
951 netlist.connect(
952 core.port(i), *almaif_ttacore_ports[portName], 0,
953 portWidth * coreId, imemInfo().mauWidth);
954
955 } else if (coreId != -1) {
956 netlist.connect(
957 core.port(i), *almaif_ttacore_ports[portName], 0,
958 portWidth * coreId, portWidth);
959 } else {
960 netlist.connect(
961 core.port(i), *almaif_ttacore_ports[portName]);
962 }
963 } else if (
964 dmem_dram_ &&
965 portName ==
966 (boost::format("fu_%s_dram_offset") % dmemInfo_.lsuName)
967 .str()) {
968 netlist.connect(
969 core.port(i), *almaifBlock_->port("db_dram_offset"));
970 }
971 }
972 }
973
974 exportUnconnectedPorts(coreId);
975 return true;
976}
AlmaIFIntegrator::exportUnconnectedPorts
void exportUnconnectedPorts(int coreId)
Definition AlmaIFIntegrator.cc:979
PlatformIntegrator::TTA_CORE_CLK
static const TCEString TTA_CORE_CLK
Definition PlatformIntegrator.hh:312
PlatformIntegrator::TTA_CORE_RSTX
static const TCEString TTA_CORE_RSTX
Definition PlatformIntegrator.hh:313
PlatformIntegrator::createMemories
virtual bool createMemories(int coreId)
Definition PlatformIntegrator.cc:553

References almaif_ttacore_ports, almaifBlock_, PlatformIntegrator::clockPort(), ProGe::Netlist::connect(), PlatformIntegrator::createMemories(), dmem_dram_, dmemInfo_, exportUnconnectedPorts(), imem_dp_, PlatformIntegrator::imemInfo(), PlatformIntegrator::integratorBlock(), MemInfo::lsuName, ProGe::NetlistPort::name(), ProGe::NetlistBlock::netlist(), ProGe::NetlistBlock::port(), ProGe::NetlistBlock::portCount(), PlatformIntegrator::resetPort(), PlatformIntegrator::TTA_CORE_CLK, and PlatformIntegrator::TTA_CORE_RSTX.

Referenced by integrateProcessor().

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◆ integrateProcessor()

void AlmaIFIntegrator::integrateProcessor ( const ProGe::NetlistBlock *  progeBlock)
virtual

Integrates the TTA core(s) generated by ProGe

Parameters
progeBlockThe toplevel netlist block created by ProGe

Implements PlatformIntegrator.

Definition at line 207 of file AlmaIFIntegrator.cc.

208 {
209
210 initPlatformNetlist(progeBlockInOldNetlist);
211 findMemories();
212 initAlmaifBlock();
213 const NetlistBlock& cores = progeBlock();
214 int coreCount = 1;
215 for (int i = 0; i < coreCount; i++) {
216 int coreId = coreCount == 1 ? -1 : i;
217 if (!integrateCore(cores, coreId)) {
218 return;
219 }
220 }
221
222 writeNewToplevel();
223
224 addAlmaifFiles();
225 addProGeFiles();
226
227 if (generateIntegratedTestbench_) {
228 generateIntegratedTestbench();
229 }
230
231 projectFileGenerator()->writeProjectFiles();
232}
AlmaIFIntegrator::integrateCore
virtual bool integrateCore(const ProGe::NetlistBlock &cores, int coreId)
Definition AlmaIFIntegrator.cc:902
PlatformIntegrator::initPlatformNetlist
virtual void initPlatformNetlist(const ProGe::NetlistBlock *progeBlock)
Definition PlatformIntegrator.cc:328
PlatformIntegrator::progeBlock
const ProGe::NetlistBlock & progeBlock() const
Definition PlatformIntegrator.cc:541
PlatformIntegrator::writeNewToplevel
virtual void writeNewToplevel()
Definition PlatformIntegrator.cc:620
ProjectFileGenerator::writeProjectFiles
virtual void writeProjectFiles()=0

References addAlmaifFiles(), PlatformIntegrator::addProGeFiles(), findMemories(), generateIntegratedTestbench(), generateIntegratedTestbench_, initAlmaifBlock(), PlatformIntegrator::initPlatformNetlist(), integrateCore(), PlatformIntegrator::progeBlock(), projectFileGenerator(), PlatformIntegrator::writeNewToplevel(), and ProjectFileGenerator::writeProjectFiles().

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◆ pinTag()

TCEString AlmaIFIntegrator::pinTag ( ) const
virtual

Implements PlatformIntegrator.

Definition at line 1157 of file AlmaIFIntegrator.cc.

1157 {
1158 return "";
1159}

◆ printInfo()

void AlmaIFIntegrator::printInfo ( std::ostream &  stream) const
virtual

Prints information about the platform

Implements PlatformIntegrator.

Definition at line 1109 of file AlmaIFIntegrator.cc.

1109 {
1110 stream
1111 << "Integrator name: AlmaIFIntegrator" << std::endl
1112 << "-----------------------------" << std::endl
1113 << "Integrates the processor core to an AXI4 bus interface according "
1114 << "to ALMARVI HW Integration Interface specification." << std::endl
1115 << "Supported instruction memory types are 'onchip' and 'none'."
1116 << std::endl
1117 << "Supported data memory types are 'onchip' and 'none'." << std::endl
1118 << "Data and Parameter memory spaces must be named '" << DMEM_NAME
1119 << "' and '" << PMEM_NAME << "' respectively." << std::endl
1120 << std::endl;
1121}

References DMEM_NAME, and PMEM_NAME.

◆ projectFileGenerator()

ProjectFileGenerator * AlmaIFIntegrator::projectFileGenerator ( ) const
virtual

Implements PlatformIntegrator.

Definition at line 1162 of file AlmaIFIntegrator.cc.

1162 {
1163 return fileGen_;
1164}

References fileGen_.

Referenced by addAlmaifFiles(), and integrateProcessor().

◆ setDeviceFamily()

void AlmaIFIntegrator::setDeviceFamily ( TCEString  devFamily)
virtual

Set the FPGA device family.

Intended for TTA IP integration. Integrator can device whether this overrides the default device family.

Implements PlatformIntegrator.

Definition at line 1135 of file AlmaIFIntegrator.cc.

1135 {
1136
1137 deviceFamily_ = devFamily;
1138}

References deviceFamily_.

◆ targetClockFrequency()

int AlmaIFIntegrator::targetClockFrequency ( ) const
virtual

Returns the target clock frequency in MHz

Reimplemented from PlatformIntegrator.

Definition at line 1152 of file AlmaIFIntegrator.cc.

1152 {
1153 return 1;
1154}

Member Data Documentation

◆ accelInstantiator_

HDLTemplateInstantiator AlmaIFIntegrator::accelInstantiator_
private

Definition at line 146 of file AlmaIFIntegrator.hh.

Referenced by addAlmaifFiles(), connectCoreMemories(), and initAlmaifBlock().

◆ ALMAIF_MODULE

const TCEString AlmaIFIntegrator::ALMAIF_MODULE = "tta_accel"
staticprivate

Definition at line 119 of file AlmaIFIntegrator.hh.

Referenced by initAlmaifBlock().

◆ almaif_ttacore_ports

std::map<TCEString, ProGe::NetlistPort*> AlmaIFIntegrator::almaif_ttacore_ports
private

Definition at line 127 of file AlmaIFIntegrator.hh.

Referenced by addPortToAlmaIFBlock(), addPortToAlmaIFBlock(), and integrateCore().

◆ almaifBlock_

ProGe::NetlistBlock* AlmaIFIntegrator::almaifBlock_
private

Definition at line 129 of file AlmaIFIntegrator.hh.

Referenced by addPortToAlmaIFBlock(), addPortToAlmaIFBlock(), connectCoreMemories(), dmemInstance(), exportUnconnectedPorts(), imemInstance(), initAlmaifBlock(), and integrateCore().

◆ AXI_AS_NAME

const TCEString AlmaIFIntegrator::AXI_AS_NAME = "axi_as"
staticprivate

Definition at line 118 of file AlmaIFIntegrator.hh.

Referenced by dmemInstance().

◆ broadcast_pmem_

bool AlmaIFIntegrator::broadcast_pmem_
private

Definition at line 151 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), and initAlmaifBlock().

◆ DEFAULT_DEVICE

const TCEString AlmaIFIntegrator::DEFAULT_DEVICE = "xc7z020clg400-1"
staticprivate

Definition at line 120 of file AlmaIFIntegrator.hh.

◆ DEFAULT_LOCAL_MEMORY_WIDTH

const int AlmaIFIntegrator::DEFAULT_LOCAL_MEMORY_WIDTH = 15
staticprivate

Definition at line 123 of file AlmaIFIntegrator.hh.

Referenced by axiAddressWidth(), and initAlmaifBlock().

◆ DEFAULT_RESERVED_PRIVATE_MEM_SIZE

const int AlmaIFIntegrator::DEFAULT_RESERVED_PRIVATE_MEM_SIZE = 2048
staticprivate

Definition at line 122 of file AlmaIFIntegrator.hh.

Referenced by initAlmaifBlock().

◆ deviceFamily_

TCEString AlmaIFIntegrator::deviceFamily_
private

Definition at line 131 of file AlmaIFIntegrator.hh.

Referenced by deviceFamily(), and setDeviceFamily().

◆ deviceName_

TCEString AlmaIFIntegrator::deviceName_
private

Definition at line 132 of file AlmaIFIntegrator.hh.

◆ dmem_dram_

bool AlmaIFIntegrator::dmem_dram_ = false
private

Definition at line 152 of file AlmaIFIntegrator.hh.

Referenced by findMemories(), initAlmaifBlock(), and integrateCore().

◆ DMEM_NAME

const TCEString AlmaIFIntegrator::DMEM_NAME = "data"
staticprivate

Definition at line 116 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and printInfo().

◆ dmemGen_

std::map<TCEString, MemoryGenerator*> AlmaIFIntegrator::dmemGen_
private

Definition at line 126 of file AlmaIFIntegrator.hh.

Referenced by dmemInstance(), and ~AlmaIFIntegrator().

◆ dmemHandled_

bool AlmaIFIntegrator::dmemHandled_
private

Definition at line 139 of file AlmaIFIntegrator.hh.

Referenced by dmemInstance().

◆ dmemInfo_

MemInfo AlmaIFIntegrator::dmemInfo_
private

Definition at line 136 of file AlmaIFIntegrator.hh.

Referenced by axiAddressWidth(), dmemInstance(), findMemories(), initAlmaifBlock(), and integrateCore().

◆ fileGen_

DefaultProjectFileGenerator* AlmaIFIntegrator::fileGen_
private

Definition at line 134 of file AlmaIFIntegrator.hh.

Referenced by projectFileGenerator().

◆ generateIntegratedTestbench_

bool AlmaIFIntegrator::generateIntegratedTestbench_ = false
private

Definition at line 155 of file AlmaIFIntegrator.hh.

Referenced by integrateProcessor().

◆ hasMinimalDebugger_

bool AlmaIFIntegrator::hasMinimalDebugger_
private

Definition at line 148 of file AlmaIFIntegrator.hh.

Referenced by addAlmaifFiles(), AlmaIFIntegrator(), and initAlmaifBlock().

◆ hasSeparateLocalMemory_

bool AlmaIFIntegrator::hasSeparateLocalMemory_ = true
private

Definition at line 149 of file AlmaIFIntegrator.hh.

Referenced by findMemories(), and initAlmaifBlock().

◆ imem_dp_

bool AlmaIFIntegrator::imem_dp_ = false
private

Definition at line 153 of file AlmaIFIntegrator.hh.

Referenced by imemInstance(), initAlmaifBlock(), and integrateCore().

◆ imemGen_

MemoryGenerator* AlmaIFIntegrator::imemGen_
private

Definition at line 125 of file AlmaIFIntegrator.hh.

Referenced by imemInstance(), and ~AlmaIFIntegrator().

◆ PMEM_NAME

const TCEString AlmaIFIntegrator::PMEM_NAME = "param"
staticprivate

Definition at line 117 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and printInfo().

◆ pmemHandled_

bool AlmaIFIntegrator::pmemHandled_
private

Definition at line 139 of file AlmaIFIntegrator.hh.

Referenced by dmemInstance().

◆ pmemInfo_

MemInfo AlmaIFIntegrator::pmemInfo_
private

Definition at line 136 of file AlmaIFIntegrator.hh.

Referenced by addAlmaifFiles(), axiAddressWidth(), dmemInstance(), findMemories(), generateIntegratedTestbench(), and initAlmaifBlock().

◆ secondDmem_

bool AlmaIFIntegrator::secondDmem_
private

Definition at line 138 of file AlmaIFIntegrator.hh.

Referenced by findMemories(), and initAlmaifBlock().

◆ secondDmemAddrw_

int AlmaIFIntegrator::secondDmemAddrw_ = 0
private

Definition at line 142 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and initAlmaifBlock().

◆ secondDmemDataw_

int AlmaIFIntegrator::secondDmemDataw_ = 0
private

Definition at line 141 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and initAlmaifBlock().

◆ secondDmemName_

std::string AlmaIFIntegrator::secondDmemName_
private

Definition at line 140 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), and findMemories().

◆ secondPmem_

bool AlmaIFIntegrator::secondPmem_
private

Definition at line 138 of file AlmaIFIntegrator.hh.

Referenced by findMemories(), and initAlmaifBlock().

◆ secondPmemAddrw_

int AlmaIFIntegrator::secondPmemAddrw_ = 0
private

Definition at line 145 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and initAlmaifBlock().

◆ secondPmemDataw_

int AlmaIFIntegrator::secondPmemDataw_ = 0
private

Definition at line 144 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), dmemInstance(), findMemories(), and initAlmaifBlock().

◆ secondPmemName_

std::string AlmaIFIntegrator::secondPmemName_
private

Definition at line 143 of file AlmaIFIntegrator.hh.

Referenced by connectCoreMemories(), and findMemories().

◆ syncReset_

bool AlmaIFIntegrator::syncReset_
private

Definition at line 150 of file AlmaIFIntegrator.hh.

Referenced by initAlmaifBlock().

The documentation for this class was generated from the following files:
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