91 endCycle_(INT_MAX), bypass_(true), dre_(true), bypassDistance_(3) {
170 bool movesRemoved =
false;
204 std::string message =
" Move(s) did not get scheduled: ";
205 for (
int i = 0; i < moves.
nodeCount(); i++) {
218 debugLog(
"All moves in the DDG didn't get scheduled.");
224 std::string wtf =
"0";
235 std::cerr <<
"rm largest cycle bigger than endCycle_!" <<
236 std::endl <<
"This may break delay slot filler!" <<
238 " end cycle: " <<
endCycle_ << std::endl;
312 bool movesRemoved =
false;
345 std::string(
"_dag.dot"));
356 debugLog(
"All moves in the DDG didn't get scheduled.");
369 <<
"No overlapping instructions."
370 <<
"Should Revert to ordinary scheduler."
383 if (overlap_count >= tripCount) {
398 if (jumpLimit != NULL) {
404 int loopCounterStep = 1;
423 (jumpOverlapCount * loopCounterStep),
440#ifdef DEBUG_REG_COPY_ADDER
441static int graphCount = 0;
461 bool operandsFailed =
true;
462 bool resultsFailed =
true;
464 int maxResult = resultsStartCycle;
466#ifdef DEBUG_REG_COPY_ADDER
469 (boost::format(
"%s_before_ddg.dot") %
ddg_->
name()).str());
476#ifdef DEBUG_REG_COPY_ADDER
477 const int tempsAdded = copies.
count_;
480#ifdef DEBUG_REG_COPY_ADDER
481 if (tempsAdded > 0) {
483 (boost::format(
"%s_after_regcopy_ddg.dot") %
ddg_->
name()).str());
496 int stopingPoint = (ii == 0) ?
499 while ((operandsFailed || resultsFailed) &&
500 resultsStartCycle >= stopingPoint) {
502 moves, resultsStartCycle, bypass, bypassLate);
503 if (maxResult != -1) {
504 resultsFailed =
false;
513 for (
int i = 0; i < moves.
nodeCount(); i++){
522 resultsFailed =
true;
523 if (bypass && bypassLate) {
526 }
else if (bypass && !bypassLate) {
529 }
else if (!bypass && bypassLate) {
541 operandsFailed =
false;
572 std::vector<MoveNode*> outputMoves;
577 for (
unsigned int i = 0; i < outputMoves.size(); i++) {
579 MoveNode& moveNode = *outputMoves[i];
585 operandsFailed =
true;
586 if (bypass && bypassLate) {
589 }
else if (bypass && !bypassLate) {
592 }
else if (!bypass && bypassLate) {
597 resultsStartCycle = std::min(maxResult, resultsStartCycle);
609 (boost::format(
"bb_%s_2_failed_scheduling.dot")
615 "Results scheduling failed for \'" + moves.
toString());
618 if (operandsFailed) {
623 (boost::format(
"bb_%s_2_scheduling.dot")
629 "Operands scheduling failed for \'" + moves.
toString());
632 for (
int i = 0; i < moves.
nodeCount(); i++) {
636#ifdef DEBUG_REG_COPY_ADDER
637 if (tempsAdded > 0) {
639 (boost::format(
"%s_after_scheduler_ddg.dot") %
642 <<
"(operation fix #" <<
ddg_->
name() <<
")" << std::endl
669 int unscheduledMoves = 0;
670 int scheduledMoves = 0;
673 for (
int i = 0; i < moves.
nodeCount(); i++) {
683 cycle = (limit < cycle) ? limit : cycle;
688 while (unscheduledMoves != scheduledMoves && counter < 5 && cycle >=0) {
701 cycle = trigger->
cycle();
715 if (triggerLatest != INT_MAX &&
716 triggerLatest > trigger->
cycle()) {
725 cycle = trigger->
cycle();
731 for (
int moveIndex = 0; moveIndex < moves.
nodeCount(); ++moveIndex) {
750 for (
int moveIndex = 0; moveIndex < moves.
nodeCount(); ++moveIndex) {
758 if (moveNode.
cycle() > cycle) {
761 std::cerr <<
"Move " << moveNode.
toString()
762 <<
" is scheduled after the trigger!" << std::endl;
770 if (scheduledMoves != unscheduledMoves) {
771 for (
int i = 0; i < moves.
nodeCount(); i++){
788 if (scheduledMoves != unscheduledMoves) {
805 MoveNodeGroup& moves,
int cycle,
bool bypass,
bool bypassLate) {
806 int maxResultCycle = cycle;
807 int tempRegLimitCycle = cycle;
808 int localMaximum = 0;
809 bool resultScheduled =
false;
810 for (
int moveIndex = 0; moveIndex < moves.
nodeCount(); ++moveIndex) {
815 bool bypassSuccess =
false;
820 (boost::format(
"Move to schedule '%s' is not "
821 "result move!") % moveNode.
toString()).str());
825 bypassSuccess =
bypassNode(moveNode, newMaximum);
827 (newMaximum > localMaximum) ? newMaximum : localMaximum;
828 if (
dre_ && bypassSuccess &&
833 resultScheduled =
true;
847 if (firstWrite != NULL) {
849 tempRegLimitCycle = firstWrite->
cycle();
853 moveNode, moveNode, tempRegLimitCycle);
857 tempRegLimitCycle = std::min(test->
cycle() -1, cycle);
861 ? std::min(localMaximum +1, tempRegLimitCycle)
875 (localMaximum < newMaximum) ? newMaximum : localMaximum;
876 localMaximum = (localMaximum > cycle) ? localMaximum : cycle;
877 int originalCycle = moveNode.
cycle();
886 resultScheduled =
true;
889 (localMaximum < moveNode.
cycle())
890 ? moveNode.
cycle() : localMaximum;
893 (moveNode.
cycle() > maxResultCycle) ?
894 moveNode.
cycle() : maxResultCycle;
898 return (resultScheduled) ? localMaximum : maxResultCycle;
912#ifdef DEBUG_REG_COPY_ADDER
915 (boost::format(
"%s_before_ddg.dot") %
ddg_->
name()).str());
926#ifdef DEBUG_REG_COPY_ADDER
927 const int tempsAdded =
931#ifdef DEBUG_REG_COPY_ADDER
935#ifdef DEBUG_REG_COPY_ADDER
936 if (tempsAdded > 0) {
938 (boost::format(
"%s_after_regcopy_ddg.dot") %
ddg_->
name()).str());
960 MoveNode& moveNode,
int latestCycle,
bool allowPredicationAndRenaming) {
965 (boost::format(
"Move '%s' is already scheduled!")
977 (boost::format(
"Move '%s' needs to be scheduled in %d,"
978 " but data dependence does not allow it!")
979 % moveNode.
toString() % ddgCycle).str());
984 if (
renamer_ != NULL && allowPredicationAndRenaming) {
985 int latestFromTrigger =
988 int minRenamedEC = std::min(
990 moveNode, ii,
true));
993 if (minRenamedEC > ddgCycle) {
995 if (minRenamedEC > ddgCycle) {
997 moveNode, ii != 0,
true,
true, minRenamedEC)) {
1000#ifdef THIS_IS_BUGGY_WITH_REGCOPY_ADDER
1005 if (limitingAdep != NULL) {
1013 *limitingAdep,
false,
true,
true)) {
1034 if (allowPredicationAndRenaming) {
1038 bool guardNeeded =
false;
1072 ddgCycle = (ddgCycle == INT_MAX) ?
endCycle_ : ddgCycle;
1076 int minCycle = std::min(latestCycle, ddgCycle);
1114 if (minCycle < earliestDDG) {
1118 if (minCycle == -1 || minCycle == INT_MAX) {
1126 std::string msg =
"Assignment of MoveNode " + moveNode.
toString();
1127 msg +=
" failed! Most likely missing Long Immediate Unit";
1128 msg +=
" or Instruction Template!";
1130 __FILE__, __LINE__,
__func__, msg);
1139 int localMaximum = 0;
1143 localMaximum = std::max(temp.
cycle(), localMaximum);
1146 if (localMaximum != 0 && localMaximum < minCycle) {
1153 localMaximum = std::max(earliestDDG, localMaximum);
1156 if (rmEarliest != -1 &&
1157 rmEarliest != INT_MAX &&
1158 rmEarliest < minCycle) {
1159 minCycle = rmEarliest;
1168 (boost::format(
"Assignment of MoveNode '%s' failed!")
1179 unsigned int epEndCycle = moveNode.
cycle() + hwop.
latency();
1197 return "Bottom-up list scheduler with a basic block scope.";
1211 "Bottom-up list basic block scheduler that uses the longest path "
1212 "information of data dependency graph to prioritize the ready list."
1213 "Assumes that the input has registers allocated and no connectivity "
1242 if (tempMove1 == NULL)
1246 if (tempMove2 != NULL) {
1253 if (firstWrite != NULL && firstWrite->
isScheduled())
1254 firstWriteCycle = firstWrite->
cycle();
1256 if (tempMove2 != NULL && tempMove2->
isScheduled()){
1257 firstWriteCycle = tempMove2->
cycle() -1;
1260 bool bypassSuccess =
false;
1301 for (DataDependenceGraph::EdgeSet::iterator i = inEdges.begin();
1302 i != inEdges.end(); ++i) {
1317 assert(tempMove == NULL &&
1318 "Multiple unscheduled moves for the operand move, should have "
1319 "max. one (the temporary move)!");
1327 if (firstRead != NULL) {
1329 lastUse = firstRead->
cycle();
1338 if (tempMove == NULL)
1343 std::cerr <<
"temp move: " << tempMove->
toString()
1378 if (tempMove1 == NULL)
1382 if (tempMove2 != NULL) {
1387 if (firstWrite != NULL) {
1389 lastUse = firstWrite->
cycle();
1393 bool bypassSuccess =
false;
1401 std::cerr <<
"not scheduled: " << tempMove1->
toString() << std::endl;
1428 for (DataDependenceGraph::NodeSet::iterator i = pred.begin();
1429 i != pred.end(); ++i) {
1437 "Multiple candidates for the temp move of result read.");
1449 int tempRegLimitCycle = cycle;
1462 if (firstWrite != NULL) {
1464 tempRegLimitCycle = firstWrite->
cycle();
1467 cycle = std::min(cycle, tempRegLimitCycle);
1494 for (DataDependenceGraph::NodeSet::iterator j =
1495 rrDestinations.begin(); j != rrDestinations.end(); j++) {
1508 node, destinationPorts)) {
1515 okDestination.insert(n);
1517 destinationPorts.clear();
1519 return okDestination;
1530 if (single == NULL) {
1532 std::vector<MoveNode*> destinationsVector =
1534 std::vector<std::pair<MoveNode*, int> > rescheduleVector;
1536 for (
unsigned int j = 0; j < destinationsVector.size(); j++) {
1538 MoveNode* dest = destinationsVector[j];
1548 rescheduleVector.push_back(
1549 std::pair<MoveNode*, int>(dest, originalCycle));
1552 for (
unsigned int i = 0; i < rescheduleVector.size(); i++) {
1554 std::pair<MoveNode*, int> dest = rescheduleVector[i];
1557 if (!dest.first->isScheduled()) {
1559 std::cerr <<
" Source: " << moveNode.
toString()
1560 <<
", Original: " << dest.first->toString() <<
1561 ", original cycle: " << dest.second << std::endl<< std::endl;
1563 assert(dest.first->isScheduled());
1584 std::cerr <<
" Source: " << moveNode.
toString()
1585 <<
", Original: " << single->
toString() <<
", original cycle: "
1586 << oCycle << std::endl;
1603 int& maxResultCycle) {
1604 bool edgesCopied =
false;
1605 unsigned int bypassCount = 0;
1606 int localMaximum = 0;
1610 unsigned int rawDestinations =
1614 if (destinations.size() > 0) {
1615 for (OrderedSet::iterator it = destinations.begin();
1616 it != destinations.end(); it++) {
1621 if (!(*it)->isScheduled() && temp == (*it)) {
1628 std::cerr <<
"\t\tSkipping temporary outgoing move " <<
1629 (*it)->toString() << std::endl;
1632 assert((*it)->isScheduled());
1633 int originalCycle = (*it)->cycle();
1636 if ((*it)->isDestinationVariable() && temp == (*it)) {
1645 (*it)->move().destination().registerFile(),
1646 (*it)->move().destination().index(),
1648 if (lastRead != NULL) {
1650 earliestLimit = lastRead->
cycle();
1654 (*it)->move().destination().registerFile(),
1655 (*it)->move().destination().index(),
1657 if (firstRead != NULL) {
1659 latestLimit = firstRead->
cycle();
1671 assert(!(*it)->isScheduled());
1674 std::cerr <<
"Merge fail. moveNode=" << moveNode.
toString()
1675 <<
", **it=" << (*it)->toString() << std::endl;
1681 if ((**it).move().source().isImmediateRegister()) {
1682 (**it).move().setSource(
1689 assert((*it)->isScheduled() ==
false);
1690 int startCycle = std::min(latestLimit, maxResultCycle);
1694 std::cerr <<
"\t\t\tCreated " << (*it)->toString()
1695 <<
" with original cycle " << originalCycle << std::endl;
1697 if (!(*it)->isScheduled() ||
1698 (*it)->cycle() > latestLimit ||
1699 (*it)->cycle() < earliestLimit ||
1700 (*it)->cycle() < originalCycle) {
1709 ((*it)->cycle() > localMaximum) ?
1710 (*it)->cycle() : localMaximum;
1726 if (rrDestinations.size() == 0 &&
1734 if (bypassCount == rawDestinations && bypassCount != 0) {
1735 maxResultCycle = localMaximum;
1747 std::map<const MoveNode*, DataDependenceGraph::NodeSet >::
1751 for (DataDependenceGraph::NodeSet::iterator i =
1752 tempMoves.begin(); i != tempMoves.end(); i++) {
1759 std::cerr <<
"\tDroping node " << node.
toString() << std::endl;
1763 copyDepsOver(node,
true,
true);
1771 for (DataDependenceGraph::NodeSet::iterator i =
1772 preds.begin(); i != preds.end(); i++) {
1775 std::map<const MoveNode*, DataDependenceGraph::NodeSet >::
1779 for (DataDependenceGraph::NodeSet::iterator i =
1780 tempMoves.begin(); i != tempMoves.end(); i++) {
1781 if ((*i)->isScheduled()) {
1785 std::cerr <<
"\tDroping temp move for node "
1786 << node.
toString() <<
", " << (*i)->toString()
1791 copyDepsOver(**i,
true,
true);
1810 predecessors.erase(&node);
1816 copyDepsOver(node,
true,
true);
1822 for (DataDependenceGraph::NodeSet::iterator iter =
1823 predecessors.begin();
1824 iter != predecessors.end(); iter++) {
1832 __FILE__, __LINE__,
__func__, msg);
1843 for (DataDependenceGraph::NodeSet::iterator i = scheduled.begin();
1844 i != scheduled.end(); ++i) {
1848 i = scheduled.begin();
1854 std::vector<MoveNode*> destinationsVector = (*it).second;
1855 for (
unsigned int k = 0; k < destinationsVector.size(); k++) {
1857 MoveNode* dest = destinationsVector[k];
1875 for (std::set<MoveNode*>::iterator i =
droppedNodes_.begin();
1916 if (triggerOperand != 0) {
1918 int latestMinCycle = -1;
1919 int firstMinCycle = INT_MAX;
1929 if (operandIndex != triggerOperand) {
1939 if (minCycle > latestMinCycle) {
1941 latestMinCycle = minCycle;
1943 if (minCycle < firstMinCycle) {
1944 firstMinCycle = minCycle;
1951 if (latestMinCycle == firstMinCycle) {
1954 if (latestMinCycle - firstMinCycle > 1) {
1955 if (lastOperand == triggerOperand) {
1960 if (lastOperand != triggerOperand) {
1988 for (DataDependenceGraph::EdgeSet::iterator i = inEdges.begin();
1989 i != inEdges.end(); i++) {
1995 if (wawPred == NULL) {
2003 if (wawPred == NULL) {
2014 for (DataDependenceGraph::NodeSet::iterator i = consumers.begin();
2015 i != consumers.end(); i++) {
2017 if (consumers2.find(mn) == consumers2.end() &&
2037 bool revert =
false;
#define abortWithError(message)
#define assert(condition)
static CmdLineOptions * cmdLineOptions()
static std::ostream & logStream()
void scheduleRRMove(MoveNode &moveNode)
virtual ~BUBasicBlockScheduler()
std::map< MoveNode *, std::vector< int >, MoveNode::Comparator > bypassDestinationsCycle_
void scheduleOperation(MoveNodeGroup &moves, BUMoveNodeSelector &selector)
bool scheduleOperandWrites(MoveNodeGroup &moves, int cycle)
bool tryToSwitchInputs(ProgramOperation &op)
bool scheduleOperand(MoveNode &, int cycle)
bool tryToOptimizeWaw(const MoveNode &moveNode)
virtual int handleLoopDDG(DataDependenceGraph &ddg, SimpleResourceManager &rm, const TTAMachine::Machine &targetMachine, int tripCount, SimpleResourceManager *prologRM=NULL, bool testOnly=false)
bool bypassNode(MoveNode &node, int &maxResultCycle)
virtual std::string longDescription() const
void undoBypass(MoveNode &node, MoveNode *single=NULL, int originalCycle=-1)
MoveNode * precedingTempMove(MoveNode ¤t)
void scheduleMove(MoveNode &move, int cycle, bool allowPredicationandRenaming)
void finalizeSchedule(MoveNode &node, BUMoveNodeSelector &selector)
std::set< MoveNode *, ltstr > OrderedSet
std::set< MoveNode * > droppedNodes_
OrderedSet findBypassDestinations(MoveNode &node)
std::map< MoveNode *, std::vector< const TTAMachine::Bus * >, MoveNode::Comparator > bypassDestinationsBus_
virtual int handleDDG(DataDependenceGraph &ddg, SimpleResourceManager &rm, const TTAMachine::Machine &targetMachine, int minCycle=0, bool testOnly=false)
virtual std::string shortDescription() const
void scheduleResultReadTempMoves(MoveNode &resultMove, MoveNode &resultRead, int lastUse)
void unscheduleAllNodes()
void scheduleInputOperandTempMoves(MoveNode &resultMove, MoveNode &resultRead)
std::map< MoveNode *, std::vector< MoveNode * >, MoveNode::Comparator > bypassDestinations_
int scheduleResultReads(MoveNodeGroup &moves, int cycle, bool bypass=false, bool bypassLate=false)
BUBasicBlockScheduler(InterPassData &data, SoftwareBypasser *bypasser=NULL, RegisterRenamer *registerRenamer=NULL)
void scheduleRRTempMoves(MoveNode ®ToRegMove, MoveNode &firstMove, int lastUse)
virtual MoveNodeGroup candidates()
virtual void notifyScheduled(MoveNode &node)
virtual void mightBeReady(MoveNode &node)
MoveNodeSelector * selector_
void unscheduleInputOperandTempMoves(MoveNode &operandMove)
SimpleResourceManager * rm_
Resource Manager of the currently scheduled BB.
static MoveNode * findTrigger(const ProgramOperation &po, const TTAMachine::Machine &mach)
void unscheduleResultReadTempMoves(MoveNode &resultMove)
const TTAMachine::Machine * targetMachine_
The target machine we are scheduling the program against.
DataDependenceGraph * ddg_
DDG of the currently scheduled BB.
std::map< const MoveNode *, DataDependenceGraph::NodeSet > scheduledTempMoves_
Stores the MoveNodes that were scheduled as temp moves during scheduling of the operand move.
int getTriggerOperand(const Operation &operation, const TTAMachine::Machine &machine)
LLVMTCECmdLineOptions * options_
int minCycle_
The earliest cycle to schedule moves in. Used to leave room for sched_yield() by the sched_yield() em...
void notifyScheduled(MoveNodeGroup &moves, MoveNodeSelector &selector)
void unschedule(MoveNode &moveNode)
MoveNode * succeedingTempMove(MoveNode ¤t)
RegisterRenamer * renamer_
void ddgSnapshot(DataDependenceGraph &ddg, const std::string &name, DataDependenceGraph::DumpFileFormat format, bool final, bool resetCounter=false) const
virtual void removeEdge(Edge &e)
virtual void removeNode(Node &node)
Node & node(const int index) const
bool hasNode(const Node &) const
virtual void dropNode(Node &node)
virtual const TCEString & name() const
virtual NodeSet predecessors(const Node &node, bool ignoreBackEdges=false, bool ignoreForwardEdges=false) const
virtual Node & tailNode(const Edge &edge) const
virtual EdgeSet inEdges(const Node &node) const
virtual void connectNodes(const Node &nTail, const Node &nHead, Edge &e)
static std::string toString(const T &source)
DependenceType dependenceType() const
EdgeReason edgeReason() const
MoveNode * firstScheduledRegisterWrite(const TTAMachine::BaseRegisterFile &rf, int registerIndex) const
int latestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegAntideps=false, bool ignoreUnscheduledSuccessors=true, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false) const
NodeSet regRawSuccessors(const MoveNode &node) const
int earliestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegWaRs=false, bool ignoreRegWaWs=false, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false, bool assumeBypassing=false) const
void copyOutgoingGuardWarEdges(const MoveNode &src, MoveNode &dst)
void unMergeUser(MoveNode &resultNode, MoveNode &mergedNode, bool loopBypass=false)
void moveFUDependenciesToTrigger(MoveNode &trigger)
NodeSet scheduledMoves() const
int smallestCycle() const
int scheduledNodeCount() const
bool mergeAndKeepUser(MoveNode &resultNode, MoveNode &userNode, bool force=false)
bool exclusingGuards(const MoveNode &mn1, const MoveNode &mn2) const
NodeSet onlyRegisterRawDestinations(const MoveNode &mn, bool allowGuardEdges=false, bool allowBackEdges=false) const
MoveNode * lastScheduledRegisterRead(const TTAMachine::BaseRegisterFile &rf, int registerIndex, int lastCycleToTest=INT_MAX) const
void copyIncomingGuardEdges(const MoveNode &src, MoveNode &dst)
MoveNode * onlyRegisterRawSource(const MoveNode &mn, int allowGuardEdges=2, int backEdges=0) const
std::pair< MoveNode *, MoveNode * > findLoopLimitAndIndex(MoveNode &jumpMove)
bool resultUsed(MoveNode &resultNode)
virtual void setCycleGrouping(bool flag)
void removeOutgoingGuardWarEdges(MoveNode &node)
EdgeSet copyDepsOver(MoveNode &node, bool anti, bool raw)
MoveNode * firstScheduledRegisterRead(const TTAMachine::BaseRegisterFile &rf, int registerIndex, int firstCycleToTest=0) const
void removeIncomingGuardEdges(MoveNode &node)
bool guardsAllowBypass(const MoveNode &defNode, const MoveNode &useNode, bool loopBypass=false)
MoveNode * findLimitingAntidependenceDestination(MoveNode &mn)
virtual void writeToDotFile(const TCEString &fileName) const
std::set< GraphNode *, typename GraphNode::Comparator > NodeSet
std::set< GraphEdge *, typename GraphEdge::Comparator > EdgeSet
virtual bool dumpDDGsDot() const
virtual bool dumpDDGsXML() const
static int canSourceWriteToAnyDestinationPort(const MoveNode &src, PortSet &ports, bool ignoreGuard=false)
std::set< const TTAMachine::Port *, const TTAMachine::MachinePart::Comparator > PortSet
MoveNode & node(int index) const
std::string toString() const
bool isOperationMove() const
int latestTriggerWriteCycle() const
bool isSourceVariable() const
ProgramOperation & sourceOperation() const
bool isDestinationOperation() const
std::string toString() const
TTAProgram::Move & move()
bool isSourceOperation() const
bool isSourceConstant() const
bool isDestinationVariable() const
ProgramOperation & destinationOperation(unsigned int index=0) const
virtual TCEString name() const
virtual bool hasSideEffects() const
virtual int affectsCount() const
virtual bool writesMemory() const
virtual int numberOfInputs() const
virtual bool canSwap(int id1, int id2) const
int outputMoveCount() const
const Operation & operation() const
int inputMoveCount() const
MoveNode & inputMove(int index) const
bool isAnyOutputAssigned()
void switchInputs(int idx1=1, int idx2=2)
MoveNode & outputMove(int index) const
void operandsScheduled(AddedRegisterCopies &copies, DataDependenceGraph &ddg)
AddedRegisterCopies addRegisterCopiesToRRMove(MoveNode &moveNode, DataDependenceGraph *ddg)
void resultsScheduled(AddedRegisterCopies &copies, DataDependenceGraph &ddg)
AddedRegisterCopies addMinimumRegisterCopies(ProgramOperation &programOperation, const TTAMachine::Machine &targetMachine, DataDependenceGraph *ddg)
bool renameDestinationRegister(MoveNode &node, bool loopScheduling, bool allowSameRf, bool differentRfOnlyDirectlyReachable, int earliestCycle=-1)
void setSelector(MoveNodeSelector *selector)
bool renameSourceRegister(MoveNode &node, bool loopScheduling, bool allowSameRf, bool differentRfOnlyDirectlyReachable, int latestCycle=INT_MAX)
void initialize(DataDependenceGraph &ddg)
virtual int bypassDistance() const
virtual bool killDeadResults() const
InterPassData & interPassData()
unsigned int unsignedValue() const
virtual int smallestCycle() const override
virtual void assign(int cycle, MoveNode &node, const TTAMachine::Bus *bus=NULL, const TTAMachine::FunctionUnit *srcFU=NULL, const TTAMachine::FunctionUnit *dstFU=NULL, int immWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1) override
void setMaxCycle(unsigned int maxCycle)
virtual int earliestCycle(MoveNode &node, const TTAMachine::Bus *bus=NULL, const TTAMachine::FunctionUnit *srcFU=NULL, const TTAMachine::FunctionUnit *dstFU=NULL, int immWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1) const override
virtual unsigned initiationInterval() const
virtual bool canTransportImmediate(const MoveNode &node, const TTAMachine::Bus *preAssignedBus=NULL) const
virtual void unassign(MoveNode &node) override
virtual int largestCycle() const override
virtual int latestCycle(MoveNode &node, const TTAMachine::Bus *bus=NULL, const TTAMachine::FunctionUnit *srcFU=NULL, const TTAMachine::FunctionUnit *dstFU=NULL, int immWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1) const override
virtual HWOperation * operation(const std::string &name) const
virtual ControlUnit * controlUnit() const
void setAnnotation(const ProgramAnnotation &annotation)
bool hasAnnotations(ProgramAnnotation::Id id=ProgramAnnotation::ANN_UNDEF_ID) const
static TTAProgram::MoveGuard * createInverseGuard(const TTAProgram::MoveGuard &mg, const TTAMachine::Bus *bus=NULL)
void setSource(Terminal *src)
MoveGuard & guard() const
bool isControlFlowMove() const
bool isUnconditional() const
Terminal & source() const
void setGuard(MoveGuard *guard)
void setBus(const TTAMachine::Bus &bus)
Terminal & destination() const
@ ANN_STACKFRAME_PROCEDURE_RETURN
precedure return jmp
@ ANN_CONNECTIVITY_MOVE
A reg to reg move that was added because of missing connectivity between the original target and dest...
virtual bool isRA() const
virtual bool isTriggering() const
virtual const TTAMachine::FunctionUnit & functionUnit() const
virtual int index() const
virtual bool equals(const Terminal &other) const =0
virtual bool isGPR() const
virtual int operationIndex() const
virtual const TTAMachine::Port & port() const
virtual const TTAMachine::RegisterFile & registerFile() const