Inheritance diagram for DefaultICDecoderGenerator:

Collaboration diagram for DefaultICDecoderGenerator:

Public Member Functions
	DefaultICDecoderGenerator (const TTAMachine::Machine &machine, const BinaryEncoding &bem)

virtual	~DefaultICDecoderGenerator ()

virtual void	completeNetlist (NetlistBlock &netlistBlock, const NetlistGenerator &generator)

void	addRV32MicroCode (NetlistBlock &netlistBlock, const NetlistGenerator &generator)

void	generateDebuggerCode (const NetlistGenerator &generator)

void	addDummyIfetchDebugPorts (const NetlistGenerator &generator)

virtual void	generate (HDL language, const std::string &dstDirectory, const NetlistGenerator &generator, const IDF::MachineImplementation &implementation, const std::string &entityString)

virtual std::set< int >	requiredRFLatencies (const TTAMachine::ImmediateUnit &iu) const

virtual void	verifyCompatibility () const

Public Member Functions inherited from ProGe::ICDecoderGeneratorPlugin
	ICDecoderGeneratorPlugin (const TTAMachine::Machine &machine, const BinaryEncoding &bem, const std::string &description)

virtual	~ICDecoderGeneratorPlugin ()

std::string	pluginDescription () const

int	recognizedParameterCount () const

std::string	recognizedParameter (int index) const

std::string	parameterDescription (const std::string &paramName) const

void	setParameter (const std::string &name, const std::string &value)

const TTAMachine::Machine &	machine () const

const BinaryEncoding &	bem () const

Private Member Functions
virtual void	writeGlobalDefinitions (HDL language, std::ostream &pkgStream) const

bool	generateDebugger (bool minimal=true) const

bool	generateBusTrace () const

bool	hasSynchronousReset () const

bool	generateLockTrace () const

bool	bypassInstructionRegister () const

int	busTraceStartingCycle () const

int	lockTraceStartingCycle () const

bool	generateNoSelfLockingFUs () const

void	addInstructioRegisterBypass (HDL language, const NetlistGenerator &generator)

int	calculateSupportedDelaySlots () const

void	readParameters ()

Static Private Member Functions
static std::string	vhdlDirection (ProGe::Direction direction)

static int	dataPortWidth (const TTAMachine::Socket &socket)

Private Attributes
NetlistBlock *	dbsmBlock

DefaultICGenerator *	icGenerator_

DefaultDecoderGenerator *	decoderGenerator_

const TTAMachine::Machine &	ttamachine_

const BinaryEncoding &	bem_

Additional Inherited Members
Protected Member Functions inherited from ProGe::ICDecoderGeneratorPlugin
void	addParameter (const std::string &name, const std::string &description)

bool	hasParameterSet (const std::string &name) const

std::string	parameterValue (const std::string &name) const

Static Protected Member Functions inherited from ProGe::ICDecoderGeneratorPlugin
static TTAMachine::Socket::Direction	convertDirection (HDB::Direction direction)

Detailed Description

Default implementation for IC/decoder generator.

Definition at line 929 of file DefaultICDecoderPlugin.cc.

Constructor & Destructor Documentation

◆ DefaultICDecoderGenerator()

DefaultICDecoderGenerator::DefaultICDecoderGenerator	(	const TTAMachine::Machine &	machine,
		const BinaryEncoding &	bem
	)

inline

Definition at line 931 of file DefaultICDecoderPlugin.cc.

        : ICDecoderGeneratorPlugin(machine, bem, PLUGIN_DESCRIPTION),
          dbsmBlock(NULL),
          icGenerator_(NULL),
          decoderGenerator_(NULL),
          ttamachine_(machine),
          bem_(bem) {
        addParameter(
            GENERATE_DEBUGGER_PARAM,
            "Generates wires to the internal hardware debugger if "
            "the value is '" + GENERATE_DEBUGGER_PARAM_INTERNAL
            + "', and to the external debugger if the value is '"
            + GENERATE_DEBUGGER_PARAM_EXTERNAL + "'. A minimal set of wires, "
            "for softreset and break, are added if the value is '"
            + GENERATE_DEBUGGER_PARAM_MINIMAL + "'.");
        addParameter(
            GENERATE_BUS_TRACE_PARAM,
            "Generates code that prints bus trace if the value is '" +
                ENABLE_FEATURE + "'.");
        addParameter(
            BUS_TRACE_STARTING_CYCLE,
            "The first cycle for which the bus trace is printed.");
        addParameter(
            GENERATE_LOCK_TRACE_PARAM,
            "Generates code that prints global lock trace if the value is"
            " '" +
                ENABLE_FEATURE + "'.");
        addParameter(
            LOCK_TRACE_STARTING_CYCLE,
            "The first cycle for which the global lock trace is printed. "
            "If value is \"" + BUS_TRACE_STARTING_CYCLE + "\" then the "
            "value is inherited from " + BUS_TRACE_STARTING_CYCLE + ".");
        addParameter(
            BYPASS_FETCHBLOCK_REG_PARAM,
            "-1 delay slot by removing instruction fetch register. "
            "'" +
                ENABLE_FEATURE + "' to enable the feature.");
 
        icGenerator_ = new DefaultICGenerator(machine);
        decoderGenerator_ = new DefaultDecoderGenerator(
            machine, bem, *icGenerator_);
    }

References ProGe::ICDecoderGeneratorPlugin::addParameter(), ProGe::ICDecoderGeneratorPlugin::bem(), BUS_TRACE_STARTING_CYCLE, BYPASS_FETCHBLOCK_REG_PARAM, decoderGenerator_, ENABLE_FEATURE, GENERATE_BUS_TRACE_PARAM, GENERATE_DEBUGGER_PARAM, GENERATE_DEBUGGER_PARAM_EXTERNAL, GENERATE_DEBUGGER_PARAM_INTERNAL, GENERATE_DEBUGGER_PARAM_MINIMAL, GENERATE_LOCK_TRACE_PARAM, icGenerator_, LOCK_TRACE_STARTING_CYCLE, and ProGe::ICDecoderGeneratorPlugin::machine().

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◆ ~DefaultICDecoderGenerator()

virtual DefaultICDecoderGenerator::~DefaultICDecoderGenerator ( )

inlinevirtual

Definition at line 975 of file DefaultICDecoderPlugin.cc.

                                         {
        delete icGenerator_;
        delete decoderGenerator_;
    }

References decoderGenerator_, and icGenerator_.

Member Function Documentation

◆ addDummyIfetchDebugPorts()

void DefaultICDecoderGenerator::addDummyIfetchDebugPorts ( const NetlistGenerator & generator )

inline

Definition at line 1370 of file DefaultICDecoderPlugin.cc.

                                                                {
        NetlistBlock* fetchBlock = &generator.instructionFetch();
        // Connect ifetch debug ports
        NetlistPort* ifetchDebugLockRqPort = new NetlistPort(
            "db_lockreq", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
        ifetchDebugLockRqPort->setToStatic(ProGe::StaticSignal::GND);
        NetlistPort* ifetchDebugResetPort = new NetlistPort(
            "db_rstx", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
        ifetchDebugResetPort->setToStatic(ProGe::StaticSignal::VCC);
        new NetlistPort(
            "db_pc", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
            *fetchBlock);
        new NetlistPort(
            "db_pc_next", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
            *fetchBlock);
        new NetlistPort(
            "db_cyclecnt", "32", 32, ProGe::BIT_VECTOR, ProGe::OUT,
            *fetchBlock);
        new NetlistPort(
            "db_lockcnt", "32", 32, ProGe::BIT_VECTOR, ProGe::OUT,
            *fetchBlock);
    }

References ProGe::BIT, ProGe::BIT_VECTOR, ProGe::StaticSignal::GND, ProGe::IN, ProGe::NetlistGenerator::instructionFetch(), ProGe::OUT, ProGe::NetlistPort::setToStatic(), and ProGe::StaticSignal::VCC.

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◆ addInstructioRegisterBypass()

void DefaultICDecoderGenerator::addInstructioRegisterBypass	(	HDL	language,
		const NetlistGenerator &	generator
	)

inlineprivate

Enables instruction register bypass feature in the instruction fetch block.

Definition at line 1835 of file DefaultICDecoderPlugin.cc.

                                                         {
        assert(
            ttamachine_.isRISCVMachine() &&
            "Instruction register by pass only implemented for RISC-V");
 
        // Todo: remove when this feature is added to debugger-fetch.
        assert(
            !generateDebugger() &&
            "addInstructionRegisterBypass(): "
            "debugger does not support Instruction Register Bypass "
            "feature yet.");
 
        NetlistBlock* ifetchBlock = &generator.instructionFetch();
 
        if (language == ProGe::VHDL) {
            ifetchBlock->setParameter(
                "bypass_fetchblock_register", "boolean", "true");
        } else if (language == ProGe::Verilog) {
            // Todo
            assert(
                false &&
                "Verilog version of instruction register bypass "
                "not implemented.");
        } else {
            assert(false && "Unknown HDL choice.");
        }
    }

References assert, generateDebugger(), ProGe::NetlistGenerator::instructionFetch(), TTAMachine::Machine::isRISCVMachine(), ProGe::NetlistBlock::setParameter(), ttamachine_, ProGe::Verilog, and ProGe::VHDL.

Referenced by generate().

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◆ addRV32MicroCode()

void DefaultICDecoderGenerator::addRV32MicroCode	(	NetlistBlock &	netlistBlock,
		const NetlistGenerator &	generator
	)

inline

Definition at line 1004 of file DefaultICDecoderPlugin.cc.

                                                                       {
        NetlistBlock& decompressor = generator.instructionDecompressor();
        NetlistBlock& decoder = generator.instructionDecoder();
        NetlistBlock& ifetch = generator.instructionFetch();
        Netlist& netlist = netlistBlock.netlist();
 
        // Change port width to 32 to match socket width
        ifetch.port("pc_in")->setWidthFormula("32");
 
        NetlistBlock* microCodeBlock = new NetlistBlock(
            "rv32_microcode_wrapper", "rv32_microcode_wrapper_i");
 
        // Adds the block to the netlist
        netlistBlock.addSubBlock(microCodeBlock);
 
        NetlistPort* decoderRISCVSimmPort = new NetlistPort(
            DefaultDecoderGenerator::RISCV_SIMM_PORT_IN_NAME, "32",
            ProGe::BIT_VECTOR, ProGe::IN, decoder);
 
        NetlistPort* clk = new NetlistPort(
            "clk", "1", ProGe::BIT, ProGe::IN, *microCodeBlock);
 
        NetlistPort* rst = new NetlistPort(
            "rstx", "1", ProGe::BIT, ProGe::IN, *microCodeBlock);
 
        NetlistPort* glock = new NetlistPort(
            "glock_in", "1", ProGe::BIT, ProGe::IN, *microCodeBlock);
 
        netlist.connect(
            *glock, *ifetch.port(DefaultDecoderGenerator::GLOCK_PORT_NAME));
 
        netlist.connect(*clk, generator.clkPort(netlistBlock));
 
        netlist.connect(*rst, generator.rstPort(netlistBlock));
 
        NetlistPort* instructionOut = new NetlistPort(
            "instruction_out", "INSTRUCTIONWIDTH", BIT_VECTOR, ProGe::OUT,
            *microCodeBlock);
 
        NetlistPort* microCodeImmOut = new NetlistPort(
            RISCV_SIMM_PORT_OUT_NAME, "32", BIT_VECTOR, ProGe::OUT,
            *microCodeBlock);
 
        NetlistPort* instructionIn = new NetlistPort(
            "instruction_in", "IMEMWIDTHINMAUS*IMEMMAUWIDTH", BIT_VECTOR,
            ProGe::IN, *microCodeBlock);
 
        netlist.connect(*microCodeImmOut, *decoderRISCVSimmPort);
 
        netlist.disconnectPorts(
            *ifetch.port(NetlistGenerator::FETCHBLOCK_PORT_NAME),
            *decompressor.port(NetlistGenerator::FETCHBLOCK_PORT_NAME));
 
        netlist.connect(
            *instructionOut,
            *decompressor.port(NetlistGenerator::FETCHBLOCK_PORT_NAME));
 
        netlist.connect(
            *ifetch.port(NetlistGenerator::FETCHBLOCK_PORT_NAME),
            *instructionIn);
 
        decompressor.port(NetlistGenerator::FETCHBLOCK_PORT_NAME)
            ->setWidthFormula("INSTRUCTIONWIDTH");
 
        NetlistPort* ifetchStallPortIFetch = new NetlistPort(
            IFETCH_STALL_PORT_NAME, "1", ProGe::BIT, ProGe::IN, ifetch);
 
        NetlistPort* ifetchStallPortMicroCode = new NetlistPort(
            IFETCH_STALL_PORT_NAME, "1", ProGe::BIT, ProGe::OUT,
            *microCodeBlock);
 
        NetlistPort* rvJumpPortMicroCode = new NetlistPort(
            "rv_jump", "1", ProGe::BIT, ProGe::OUT, *microCodeBlock);
 
        NetlistPort* rvAuipcPortMicroCode = new NetlistPort(
            "rv_auipc", "1", ProGe::BIT, ProGe::OUT, *microCodeBlock);
 
        NetlistPort* rvOffsetPortMicroCode = new NetlistPort(
            "rv_offset", "32", BIT_VECTOR, ProGe::OUT, *microCodeBlock);
 
        NetlistPort* rvOffsetPortIfetch =
            new NetlistPort("rv_offset", "32", BIT_VECTOR, ProGe::IN, ifetch);
 
        NetlistPort* rvJumpPortIfetch =
            new NetlistPort("rv_jump", "1", ProGe::BIT, ProGe::IN, ifetch);
 
        NetlistPort* rvAuipcPortIfetch =
            new NetlistPort("rv_auipc", "1", ProGe::BIT, ProGe::IN, ifetch);
 
        netlist.connect(*rvJumpPortMicroCode, *rvJumpPortIfetch);
        netlist.connect(*rvAuipcPortMicroCode, *rvAuipcPortIfetch);
        netlist.connect(*rvOffsetPortMicroCode, *rvOffsetPortIfetch);
 
        netlist.connect(*ifetchStallPortMicroCode, *ifetchStallPortIFetch);
    }

References ProGe::NetlistBlock::addSubBlock(), ProGe::BIT, ProGe::BIT_VECTOR, ProGe::NetlistGenerator::clkPort(), ProGe::Netlist::connect(), ProGe::Netlist::disconnectPorts(), ProGe::NetlistGenerator::FETCHBLOCK_PORT_NAME, DefaultDecoderGenerator::GLOCK_PORT_NAME, IFETCH_STALL_PORT_NAME, ProGe::IN, ProGe::NetlistGenerator::instructionDecoder(), ProGe::NetlistGenerator::instructionDecompressor(), ProGe::NetlistGenerator::instructionFetch(), ProGe::NetlistBlock::netlist(), ProGe::OUT, ProGe::NetlistBlock::port(), DefaultDecoderGenerator::RISCV_SIMM_PORT_IN_NAME, RISCV_SIMM_PORT_OUT_NAME, ProGe::NetlistGenerator::rstPort(), and ProGe::NetlistPort::setWidthFormula().

Referenced by completeNetlist().

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◆ busTraceStartingCycle()

int DefaultICDecoderGenerator::busTraceStartingCycle ( ) const

inlineprivate

Returns the starting cycle to be written to the bus trace given as parameter.

Returns: The starting cycle.

Definition at line 1740 of file DefaultICDecoderPlugin.cc.

                                      {
        if (!hasParameterSet(BUS_TRACE_STARTING_CYCLE)) {
            return 0;
        } else {
            string paramValue = parameterValue(BUS_TRACE_STARTING_CYCLE);
            try {
                unsigned int cycle = Conversion::toUnsignedInt(paramValue);
                return cycle;
            } catch (const Exception&) {
                return 0;
            }
        }
    }

References BUS_TRACE_STARTING_CYCLE, ProGe::ICDecoderGeneratorPlugin::hasParameterSet(), ProGe::ICDecoderGeneratorPlugin::parameterValue(), and Conversion::toUnsignedInt().

Referenced by generate(), lockTraceStartingCycle(), and readParameters().

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◆ bypassInstructionRegister()

bool DefaultICDecoderGenerator::bypassInstructionRegister ( ) const

inlineprivate

Tells whether instruction register should be left generated (true).

Definition at line 1721 of file DefaultICDecoderPlugin.cc.

                                      {
        if (!hasParameterSet(BYPASS_FETCHBLOCK_REG_PARAM)) {
            return false;
        } else {
            string paramValue = parameterValue(BYPASS_FETCHBLOCK_REG_PARAM);
            if (paramValue == BYPASS_FETCHBLOCK_REG_PARAM_YES) {
                return true;
            } else {
                return false;
            }
        }
    }

References BYPASS_FETCHBLOCK_REG_PARAM, BYPASS_FETCHBLOCK_REG_PARAM_YES, ProGe::ICDecoderGeneratorPlugin::hasParameterSet(), and ProGe::ICDecoderGeneratorPlugin::parameterValue().

Referenced by calculateSupportedDelaySlots(), and generate().

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◆ calculateSupportedDelaySlots()

int DefaultICDecoderGenerator::calculateSupportedDelaySlots ( ) const

inlineprivate

Return number of required delay slots. By default the number is three but can be reduced or increased by options.

Definition at line 1869 of file DefaultICDecoderPlugin.cc.

                                         {
        int delaySlots = 3;
        if (bypassInstructionRegister()) {
            delaySlots -= 1;
        }
        return delaySlots;
    }

References bypassInstructionRegister().

Referenced by verifyCompatibility().

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◆ completeNetlist()

virtual void DefaultICDecoderGenerator::completeNetlist	(	NetlistBlock &	netlistBlock,
		const NetlistGenerator &	generator
	)

inlinevirtual

Completes the given netlist by adding IC block and completing the decoder block by adding the ports connected to IC. Connects also IC to all the units in the machine.

Parameters

The	netlist to complete.
generator	The netlist generator which generated the netlist.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 989 of file DefaultICDecoderPlugin.cc.

                                                                       {
        // add interconnection network to the netlist and connect it to the 
        // units
        icGenerator_->addICToNetlist(generator, netlistBlock);
 
        // complete the decoder block and connect it to the IC and units
        decoderGenerator_->completeDecoderBlock(generator, netlistBlock);
 
        if (ttamachine_.isRISCVMachine()) {
            addRV32MicroCode(netlistBlock, generator);
        }
    }

References DefaultICGenerator::addICToNetlist(), addRV32MicroCode(), DefaultDecoderGenerator::completeDecoderBlock(), decoderGenerator_, icGenerator_, TTAMachine::Machine::isRISCVMachine(), and ttamachine_.

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◆ dataPortWidth()

static int DefaultICDecoderGenerator::dataPortWidth ( const TTAMachine::Socket & socket )

inlinestaticprivate

Calculates the data port width of the given socket.

Parameters

socket The socket.

Returns: The width of the data port.

Definition at line 1818 of file DefaultICDecoderPlugin.cc.

                                                             {
        int ports = socket.portCount();
        int width(0);
        for (int i = 0; i < ports; i++) {
            Port* port = socket.port(i);
            if (port->width() > width) {
                width = port->width();
            }
        }
        return width;
    }

References TTAMachine::Socket::port(), TTAMachine::Socket::portCount(), and TTAMachine::Port::width().

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◆ generate()

virtual void DefaultICDecoderGenerator::generate	(	HDL	language,
		const std::string &	dstDirectory,
		const NetlistGenerator &	generator,
		const IDF::MachineImplementation &	implementation,
		const std::string &	entityString
	)

inlinevirtual

Generates the interconnection network and instruction decoder to the given destination directory.

Parameters

dstDirectory	The destination directory.
generator	The netlist generator that generated the netlist.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1401 of file DefaultICDecoderPlugin.cc.

                                       {
        const string DS = FileSystem::DIRECTORY_SEPARATOR;
        const string templateDir = Environment::dataDirPath("ProGe");
 
        BlockSourceCopier copier(implementation, entityString, language);
        MachineInfo::OperationSet cuOps =
            MachineInfo::getOpset(*generator.context().adf().controlUnit());
        Path proGeDataDir(Environment::dataDirPath("ProGe"));
        HDLTemplateInstantiator& instantiator =
            copier.getTemplateInstatiator();
 
        if (ttamachine_.isRISCVMachine()) {
            instantiator.replacePlaceholder(
                "ifetch-stall-cond",
                " and " + IFETCH_STALL_PORT_NAME + " = '0'");
            instantiator.replacePlaceholder(
                "ifetch-stall-port-declarations",
                IFETCH_STALL_PORT_NAME + " : in std_logic;");
 
            ProGe::RV32MicroCodeGenerator* microCodeGen =
                new RV32MicroCodeGenerator(ttamachine_, bem_, entityString);
            microCodeGen->setBypassInstructionRegister(
                bypassInstructionRegister());
            microCodeGen->generateRTL(instantiator, dstDirectory);
        }
 
        if (generateBusTrace()) {
            icGenerator_->setGenerateBusTrace(true);
            icGenerator_->setBusTraceStartingCycle(busTraceStartingCycle());
        } else {
            icGenerator_->setGenerateBusTrace(false);
        }
 
        try {
            // Check for illegal combinations in fetch/decode unit options
 
            if (!generateDebugger()) {
                // Signal declarations as a stand-in for debug ports
                instantiator.replacePlaceholderFromFile(
                    "db-signal-declarations",
                    proGeDataDir /
                        std::string("no_debug_signal_declaration.snippet"));
            }
 
            if (hasSynchronousReset()) {
                if (language == VHDL) {
                    generator.instructionFetch().setParameter(
                        "sync_reset_g", "boolean", "true");
                    instantiator.replacePlaceholder("sync-waitlist", "clk");
                } else {  // language == Verilog
                    instantiator.replacePlaceholder(
                        "update-condition", "always@(posedge clk)");
                }
            } else {
                if (language == VHDL) {
                    instantiator.replacePlaceholder(
                        "sync-waitlist", "clk, rstx");
                } else {  // language == Verilog
                    instantiator.replacePlaceholder(
                        "update-condition",
                        "always@(posedge clk or negedge rstx)");
                }
            }
 
            if (generateNoSelfLockingFUs()) {
                decoderGenerator_->setGenerateNoLoopbackGlock(true);
                if (language == VHDL) {
                    generator.instructionFetch().setParameter(
                        "no_glock_loopback_g", "std_logic", "'1'");
                }  // todo verilog version
            }
 
            // Set the pc opcode port width
            std::size_t reqOpcodeWidth =
                CUOpcodeGenerator::gcuOpcodeWidth(ttamachine_);
            instantiator.replacePlaceholder(
                "pc-opcode-len", Conversion::toString(reqOpcodeWidth - 1));
 
            instantiator.replacePlaceholderFromFile(
                "default-instr-reg-write",
                Path(
                    proGeDataDir /
                    std::string("default-instr-reg-write.snippet")));
 
            // Next PC process sensitivity list
            std::string sensitivityStringPCBypassed =
                "pc_in, pc_reg, increased_pc        ";
            std::string sensitivityStringPCNotBypassed = "";
            // Complete the default sensitivity list
            sensitivityStringPCBypassed += ",\n pc_load, pc_opcode";
            instantiator.replacePlaceholder(  // This is bypassed too
                "pc-sensitivity-list-pc-bypass", sensitivityStringPCBypassed);
 
            // Next PC signal assign condition
            std::string conditionString =
                "pc_load = '1' and ((unsigned(pc_opcode) = IFE_CALL or \n"
                "    unsigned(pc_opcode) = IFE_JUMP))\n";
            instantiator.replacePlaceholder(
                "not-bypassed-next-pc-condition", conditionString);
 
            if (generateDebugger()) {  // DEBUGTODO
                if (language != VHDL) {
                    std::string errorMsg =
                        "Language not set to VHDL when HW debugger is in "
                        "use.";
                    throw Exception(__FILE__, __LINE__, __func__, errorMsg);
                }
 
                generator.instructionFetch().setParameter(
                    "debug_logic_g", "boolean", "true");
                if (parameterValue(GENERATE_DEBUGGER_PARAM) ==
                    GENERATE_DEBUGGER_PARAM_MINIMAL) {
                    instantiator.replacePlaceholderFromFile(
                        "db-port-declarations",
                        Path(
                            proGeDataDir /
                            std::string(
                                "debug_minimal_port_declaration.snippet")));
                    instantiator.replacePlaceholderFromFile(
                        "db-signal-declarations",
                        Path(
                            proGeDataDir /
                            std::string(
                                "debug_minimal_signal_declaration.snippet")));
                } else {
                    instantiator.replacePlaceholderFromFile(
                        "db-port-declarations",
                        Path(
                            proGeDataDir /
                            std::string("debug_port_declaration.snippet")));
                    instantiator.replacePlaceholderFromFile(
                        "db-signal-declarations",
                        Path(
                            proGeDataDir /
                            std::string("debug_signal_declaration.snippet")));
                }
                copier.instantiateHDLTemplate(
                    templateDir + DS + "ifetch." +
                        (language == VHDL ? "vhdl" : "v") + ".tmpl",
                    dstDirectory,
                    std::string("ifetch.") +
                        (language == VHDL ? "vhdl" : "v"));
            } else {
                copier.instantiateHDLTemplate(
                    templateDir + DS + "ifetch." +
                        (language == VHDL ? "vhdl" : "v") + ".tmpl",
                    dstDirectory,
                    std::string("ifetch.") +
                        (language == VHDL ? "vhdl" : "v"));
            }
        } catch (const Exception& e) {
            abortWithError(e.errorMessage());
        }
 
        if (bypassInstructionRegister()) {
            if (language != VHDL) {
                std::string errorMsg =
                    "Instruction register bypass is not supported for "
                    "given HDL.";
                throw Exception(__FILE__, __LINE__, __func__, errorMsg);
            }
 
            addInstructioRegisterBypass(language, generator);
        }
 
        // generate the IC
        icGenerator_->SetHDL(language);
        icGenerator_->generateInterconnectionNetwork(dstDirectory);
        // generate the decoder
        decoderGenerator_->SetHDL(language);
        decoderGenerator_->generateInstructionDecoder(generator, dstDirectory);
 
        if (generateDebugger()) {
            if (language != VHDL) {
                std::string errorMsg =
                    "Language not set to VHDL when HW debugger is in use.";
                throw Exception(__FILE__, __LINE__, __func__, errorMsg);
            } else {
                generateDebuggerCode(generator);
            }
        }
        if (ttamachine_.isRISCVMachine()) {
            copier.instantiateHDLTemplate(
                templateDir + DS + "rv32_ifetch.vhdl.tmpl", dstDirectory,
                "ifetch.vhdl");
        } else {
            copier.instantiateHDLTemplate(
                templateDir + DS + "ifetch.vhdl.tmpl", dstDirectory,
                "ifetch.vhdl");
        }
    }

References __func__, abortWithError, addInstructioRegisterBypass(), ProGe::ProGeContext::adf(), bem_, busTraceStartingCycle(), bypassInstructionRegister(), ProGe::NetlistGenerator::context(), TTAMachine::Machine::controlUnit(), Environment::dataDirPath(), decoderGenerator_, FileSystem::DIRECTORY_SEPARATOR, DS, Exception::errorMessage(), ProGe::CUOpcodeGenerator::gcuOpcodeWidth(), GENERATE_DEBUGGER_PARAM, GENERATE_DEBUGGER_PARAM_MINIMAL, generateBusTrace(), generateDebugger(), generateDebuggerCode(), DefaultDecoderGenerator::generateInstructionDecoder(), DefaultICGenerator::generateInterconnectionNetwork(), generateNoSelfLockingFUs(), ProGe::RV32MicroCodeGenerator::generateRTL(), MachineInfo::getOpset(), ProGe::BlockSourceCopier::getTemplateInstatiator(), hasSynchronousReset(), icGenerator_, IFETCH_STALL_PORT_NAME, implementation, ProGe::BlockSourceCopier::instantiateHDLTemplate(), ProGe::NetlistGenerator::instructionFetch(), TTAMachine::Machine::isRISCVMachine(), ProGe::ICDecoderGeneratorPlugin::parameterValue(), HDLTemplateInstantiator::replacePlaceholder(), HDLTemplateInstantiator::replacePlaceholderFromFile(), DefaultICGenerator::setBusTraceStartingCycle(), ProGe::RV32MicroCodeGenerator::setBypassInstructionRegister(), DefaultICGenerator::setGenerateBusTrace(), DefaultDecoderGenerator::setGenerateNoLoopbackGlock(), DefaultDecoderGenerator::SetHDL(), DefaultICGenerator::SetHDL(), ProGe::NetlistBlock::setParameter(), Conversion::toString(), ttamachine_, and ProGe::VHDL.

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◆ generateBusTrace()

bool DefaultICDecoderGenerator::generateBusTrace ( ) const

inlineprivate

Tells whether IC generator should generate bus tracing code.

Returns: True if IC generator should generate the code.

Definition at line 1680 of file DefaultICDecoderPlugin.cc.

                                  {
        if (!hasParameterSet(GENERATE_BUS_TRACE_PARAM)) {
            return false;
        } else {
            string paramValue = parameterValue(GENERATE_BUS_TRACE_PARAM);
            if (paramValue == GENERATE_BUS_TRACE_PARAM_YES) {
                return true;
            } else {
                return false;
            }
        }
    }

References GENERATE_BUS_TRACE_PARAM, GENERATE_BUS_TRACE_PARAM_YES, ProGe::ICDecoderGeneratorPlugin::hasParameterSet(), and ProGe::ICDecoderGeneratorPlugin::parameterValue().

Referenced by generate(), and readParameters().

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◆ generateDebugger()

bool DefaultICDecoderGenerator::generateDebugger ( bool minimal = true ) const

inlineprivate

Tells whether IC generator should generate debug interface code.

Returns: True if IC generator should generate the code.

Definition at line 1659 of file DefaultICDecoderPlugin.cc.

                                                     {
        if (!hasParameterSet(GENERATE_DEBUGGER_PARAM)) {
            return false;
        } else {
            string paramValue = parameterValue(GENERATE_DEBUGGER_PARAM);
            if (paramValue == GENERATE_DEBUGGER_PARAM_YES ||
                paramValue == GENERATE_DEBUGGER_PARAM_INTERNAL ||
                paramValue == GENERATE_DEBUGGER_PARAM_EXTERNAL ||
                (paramValue == GENERATE_DEBUGGER_PARAM_MINIMAL && minimal)) {
                return true;
            } else {
                return false;
            }
        }
    }

References GENERATE_DEBUGGER_PARAM, GENERATE_DEBUGGER_PARAM_EXTERNAL, GENERATE_DEBUGGER_PARAM_INTERNAL, GENERATE_DEBUGGER_PARAM_MINIMAL, GENERATE_DEBUGGER_PARAM_YES, ProGe::ICDecoderGeneratorPlugin::hasParameterSet(), and ProGe::ICDecoderGeneratorPlugin::parameterValue().

Referenced by addInstructioRegisterBypass(), generate(), generateDebuggerCode(), and readParameters().

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◆ generateDebuggerCode()

void DefaultICDecoderGenerator::generateDebuggerCode ( const NetlistGenerator & generator )

inline

Definition at line 1101 of file DefaultICDecoderPlugin.cc.

                                                                 {
        assert(
            generateDebugger() &&
            "Entered debugger connection generation without cause.");
 
        NetlistBlock* decoderBlock = &generator.instructionDecoder();
        NetlistBlock& toplevelBlock = decoderBlock->parentBlock();
        std::string addrWidthFormula = generator.gcuReturnAddressInPort()
            .widthFormula();
        NetlistBlock* fetchBlock = &generator.instructionFetch();
        NetlistBlock* icBlock = NULL;
 
        bool is_external = false, is_internal = false, is_minimal = false;
 
        if (parameterValue(GENERATE_DEBUGGER_PARAM) ==
            GENERATE_DEBUGGER_PARAM_EXTERNAL) {
              is_external = true;
        } else if (parameterValue(GENERATE_DEBUGGER_PARAM) ==
            GENERATE_DEBUGGER_PARAM_MINIMAL) {
              is_minimal = true;
        } else {
              is_internal = true;
        }
 
        for (std::size_t i = 0; i < toplevelBlock.subBlockCount(); i++) {
            icBlock = &toplevelBlock.subBlock(i);
            if (icBlock->instanceName() == "ic")
                break;
            if (icBlock->moduleName() == "ic")
                break;
        }
 
        if (is_internal) {
            //Include debugger package with width constants in tta0.vhdl
            toplevelBlock.addPackage("debugger_if");
        }
 
        NetlistPort* ttaResetPort = new NetlistPort(
            "db_tta_nreset", "1", BIT, ProGe::IN, toplevelBlock);
        NetlistPort *ttaLockcountPort = new NetlistPort("db_lockcnt",
            "64", ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
        NetlistPort *ttaCyclecountPort = new NetlistPort("db_cyclecnt",
            "64", ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
 
        NetlistPort *ttaPCPort = new NetlistPort("db_pc",
            "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
 
        if (is_minimal || is_external) {
 
            NetlistPort* dbGlockReqPort = new NetlistPort(
                "db_lockrq", "1", BIT, ProGe::IN, toplevelBlock);
 
            // Connect to the highest bit of decoder lockrq vector, others are
            // already connected
            NetlistPort* decoderGlockReqPort =
                decoderBlock->port("lock_req");
            int bit = decoderGenerator_->glockRequestWidth()-1;
            toplevelBlock.netlist().connect(
                *dbGlockReqPort, *decoderGlockReqPort, 0, bit, 1);
 
            // Connect ifetch debug ports
            NetlistPort* ifetchDebugResetPort = new NetlistPort(
                "db_rstx", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
            toplevelBlock.netlist().connect(*ttaResetPort,
                                            *ifetchDebugResetPort);
 
            NetlistPort* ifetchDebugLockRqPort = new NetlistPort(
                "db_lockreq", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
            toplevelBlock.netlist().connect(*dbGlockReqPort,
                *ifetchDebugLockRqPort);
 
            NetlistPort* ifetchCyclecountPort = new NetlistPort(
                "db_cyclecnt", "64", 64, ProGe::BIT_VECTOR, ProGe::OUT,
                *fetchBlock);
            toplevelBlock.netlist().connect(
                *ifetchCyclecountPort, *ttaCyclecountPort);
            NetlistPort* ifetchLockcountPort = new NetlistPort(
                "db_lockcnt", "64", 64, ProGe::BIT_VECTOR, ProGe::OUT,
                *fetchBlock);
            toplevelBlock.netlist().connect(
                *ifetchLockcountPort, *ttaLockcountPort);
 
            NetlistPort* ifetchPCPort = new NetlistPort(
                "db_pc", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
                *fetchBlock);
            toplevelBlock.netlist().connect(*ifetchPCPort, *ttaPCPort);
        }
        if (!is_minimal) {
            //Add debugger interface ports to tta0 entity
            NetlistPort *ttaPCStartPort = new NetlistPort("db_pc_start",
                "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::IN, toplevelBlock);
            NetlistPort *ttaBustracePort = new NetlistPort("db_bustraces",
                "BUSTRACE_WIDTH", ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
 
            // Connect bustraces out and away
            NetlistPort* icBustracePort = icBlock->port("db_bustraces");
            assert(icBustracePort);
            toplevelBlock.netlist().connect(
                *icBustracePort, *ttaBustracePort);
 
            if (is_external) {
                NetlistPort* dbPCNextPort = new NetlistPort(
                    "db_pc_next", "IMEMADDRWIDTH",
                    ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
 
                NetlistPort* ifetchPCStartPort = new NetlistPort(
                    "db_pc_start", "IMEMADDRWIDTH", ProGe::BIT_VECTOR,
                    ProGe::IN, *fetchBlock);
                toplevelBlock.netlist().connect(*ifetchPCStartPort,
                                                *ttaPCStartPort);
                NetlistPort* ifetchPCNextPort = new NetlistPort(
                    "db_pc_next", "IMEMADDRWIDTH", ProGe::BIT_VECTOR,
                    ProGe::OUT, *fetchBlock);
                toplevelBlock.netlist().connect(*ifetchPCNextPort,
                                                *dbPCNextPort);
 
            } else if (is_internal) { // Generate internal debugger
                NetlistPort* ttaBpEnaPort = new NetlistPort(
                    "db_bp_ena", "1+db_breakpoints",
                    ProGe::BIT_VECTOR, ProGe::IN, toplevelBlock);
                NetlistPort* ttaBp0Port = new NetlistPort(
                    "bp_target_cc", "db_breakpoints_cc*db_data_width",
                    ProGe::BIT_VECTOR, ProGe::IN, toplevelBlock);
                NetlistPort* ttaBp41Port = new NetlistPort(
                    "bp_target_pc", "db_breakpoints_pc*IMEMADDRWIDTH",
                    ProGe::BIT_VECTOR, ProGe::IN,
                    toplevelBlock);
                NetlistPort* ttaBpHitPort = new NetlistPort(
                    "db_bp_hit", "2+db_breakpoints",
                    ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
                NetlistPort* ttaContinuePort = new NetlistPort(
                    "db_tta_continue", "1", BIT, ProGe::IN, toplevelBlock);
                NetlistPort* ttaForceBreakPort = new NetlistPort(
                    "db_tta_forcebreak", "1", BIT, ProGe::IN, toplevelBlock);
                NetlistPort* ttaStdoutBreakPort = new NetlistPort(
                    "db_tta_stdoutbreak", "1", BIT, ProGe::IN, toplevelBlock);
 
                //Build and connect the debugger state machine block in tta0.vhdl
                dbsmBlock = new NetlistBlock("dbsm", "dbsm_1");
                toplevelBlock.addSubBlock(dbsmBlock);
 
                dbsmBlock->setParameter("cyclecnt_width_g", "integer",
                                        "db_data_width");
                dbsmBlock->setParameter("pc_width_g", "integer",
                                        "IMEMADDRWIDTH");
 
                NetlistPort* dbsmClkPort = new NetlistPort(
                    "clk", "1", BIT, ProGe::IN, *dbsmBlock);
                toplevelBlock.netlist().connect(
                    *dbsmClkPort, generator.clkPort(toplevelBlock));
 
                NetlistPort* dbsmNresetPort = new NetlistPort(
                    "nreset", "1", BIT, ProGe::IN, *dbsmBlock);
                toplevelBlock.netlist().connect(
                    *dbsmNresetPort, generator.rstPort(toplevelBlock));
 
                NetlistPort* dbsmBpEnaPort = new NetlistPort(
                    "bp_ena", "1+db_breakpoints",
                    ProGe::BIT_VECTOR, ProGe::IN, *dbsmBlock);
                toplevelBlock.netlist().connect(*ttaBpEnaPort, *dbsmBpEnaPort);
 
                NetlistPort* dbsmBp0Port = new NetlistPort(
                    "bp_target_cc", "db_breakpoints_cc*cyclecnt_width_g",
                    ProGe::BIT_VECTOR,
                    ProGe::IN, *dbsmBlock);
                toplevelBlock.netlist().connect(*ttaBp0Port, *dbsmBp0Port);
 
                NetlistPort* dbsmCyclecountPort = new NetlistPort(
                    "cyclecnt", "cyclecnt_width_g", ProGe::BIT_VECTOR,
                    ProGe::IN, *dbsmBlock);
 
                NetlistPort* dbsmBp41Port = new NetlistPort(
                    "bp_target_pc", "db_breakpoints_pc*IMEMADDRWIDTH",
                    ProGe::BIT_VECTOR, ProGe::IN, *dbsmBlock);
                toplevelBlock.netlist().connect(*ttaBp41Port, *dbsmBp41Port);
 
                NetlistPort* dbsmPCNextPort = new NetlistPort(
                    "pc_next", "IMEMADDRWIDTH", ProGe::BIT_VECTOR,
                    ProGe::IN, *dbsmBlock);
 
                NetlistPort* dbsmContinuePort = new NetlistPort(
                    "tta_continue", "1", BIT, ProGe::IN, *dbsmBlock);
                toplevelBlock.netlist().connect(
                    *ttaContinuePort, *dbsmContinuePort);
 
                NetlistPort* dbsmForceBreakPort = new NetlistPort(
                    "tta_forcebreak", "1", BIT, ProGe::IN, *dbsmBlock);
                toplevelBlock.netlist().connect(*ttaForceBreakPort,
                    *dbsmForceBreakPort);
 
                NetlistPort* dbsmStdoutBreakPort = new NetlistPort(
                    "tta_stdoutbreak", "1", BIT, ProGe::IN, *dbsmBlock);
                toplevelBlock.netlist().connect(
                    *ttaStdoutBreakPort, *dbsmStdoutBreakPort);
 
                NetlistPort* dbsmBpHitPort = new NetlistPort(
                    "bp_hit", "2+db_breakpoints",
                    ProGe::BIT_VECTOR, ProGe::OUT, *dbsmBlock);
                toplevelBlock.netlist().connect(*ttaBpHitPort, *dbsmBpHitPort);
 
                NetlistPort* dbsmExtlockPort = new NetlistPort(
                    "extlock", "1", BIT, ProGe::IN, *dbsmBlock);
                toplevelBlock.netlist().connect(
                    *toplevelBlock.port("busy"), *dbsmExtlockPort);
 
 
                // Connect to the highest bit of decoder lockrq vector, others are
                // already connected
                NetlistPort* dbsmGlockReqPort = new NetlistPort(
                    "bp_lockrq", "1", BIT, ProGe::OUT, *dbsmBlock);
                NetlistPort* decoderGlockReqPort =
                    decoderBlock->port("lock_req");
                int bit = decoderGenerator_->glockRequestWidth()-1;
                toplevelBlock.netlist().connect(
                    *dbsmGlockReqPort, *decoderGlockReqPort, 0, bit, 1);
 
                // Connect ifetch debug ports
                NetlistPort* ifetchDebugLockRqPort = new NetlistPort(
                    "db_lockreq", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
                toplevelBlock.netlist().connect(*dbsmGlockReqPort,
                    *ifetchDebugLockRqPort);
                NetlistPort* ifetchDebugResetPort = new NetlistPort(
                    "db_rstx", "1", 1, ProGe::BIT, ProGe::IN, *fetchBlock);
                toplevelBlock.netlist().connect(*ttaResetPort,
                    *ifetchDebugResetPort);
                NetlistPort* ifetchPCStartPort = new NetlistPort(
                    "db_pc_start", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::IN,
                    *fetchBlock);
                toplevelBlock.netlist().connect(*ifetchPCStartPort,
                                                *ttaPCStartPort);
                NetlistPort* ifetchPCPort = new NetlistPort(
                    "db_pc", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
                    *fetchBlock);
                toplevelBlock.netlist().connect(*ifetchPCPort, *ttaPCPort);
                NetlistPort* ifetchPCNextPort = new NetlistPort(
                    "db_pc_next", "IMEMADDRWIDTH", ProGe::BIT_VECTOR, ProGe::OUT,
                    *fetchBlock);
                toplevelBlock.netlist().connect(
                    *ifetchPCNextPort, *dbsmPCNextPort);
                NetlistPort* ifetchCyclecountPort = new NetlistPort(
                    "db_cyclecnt", "64", 64, ProGe::BIT_VECTOR, ProGe::OUT,
                    *fetchBlock);
                toplevelBlock.netlist().connect(
                    *ifetchCyclecountPort, *ttaCyclecountPort);
                toplevelBlock.netlist().connect(
                    *ifetchCyclecountPort, *dbsmCyclecountPort);
                NetlistPort* ifetchLockcountPort = new NetlistPort(
                    "db_lockcnt", "64", 64, ProGe::BIT_VECTOR, ProGe::OUT,
                    *fetchBlock);
                toplevelBlock.netlist().connect(
                    *ifetchLockcountPort, *ttaLockcountPort);
                NetlistPort *ttaInstrPort = new NetlistPort(
                    "db_instr", "IMEMWIDTHINMAUS*IMEMMAUWIDTH",
                    ProGe::BIT_VECTOR, ProGe::OUT, toplevelBlock);
                NetlistPort* ifetchFetchblockPort =
                    fetchBlock->port("fetchblock");
                toplevelBlock.netlist().connect(
                    *ifetchFetchblockPort, *ttaInstrPort);
 
            }
        }
 
        // Connect decoder softreset
        NetlistPort* decoderDBResetPort = decoderBlock->port("db_tta_nreset");
        decoderDBResetPort->unsetStatic();
        toplevelBlock.netlist().connect(*ttaResetPort, *decoderDBResetPort);
    }

Referenced by generate().

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◆ generateLockTrace()

bool DefaultICDecoderGenerator::generateLockTrace ( ) const

inlineprivate

Tells whether IC generator should generate global lock tracing code.

Returns: True if IC generator should generate the code.

Definition at line 1704 of file DefaultICDecoderPlugin.cc.

                                   {
        if (!hasParameterSet(GENERATE_LOCK_TRACE_PARAM)) {
            return false;
        } else {
            string paramValue = parameterValue(GENERATE_LOCK_TRACE_PARAM);
            if (paramValue == GENERATE_LOCK_TRACE_PARAM_YES) {
                return true;
            } else {
                return false;
            }
        }
    }

References GENERATE_LOCK_TRACE_PARAM, GENERATE_LOCK_TRACE_PARAM_YES, ProGe::ICDecoderGeneratorPlugin::hasParameterSet(), and ProGe::ICDecoderGeneratorPlugin::parameterValue().

Referenced by readParameters().

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◆ generateNoSelfLockingFUs()

bool DefaultICDecoderGenerator::generateNoSelfLockingFUs ( ) const

inlineprivate

Definition at line 1783 of file DefaultICDecoderPlugin.cc.

                                     {
        if (!hasParameterSet(NO_SELF_LOCKING_PARAM)) {
            return false;
        } else {
            string paramValue = parameterValue(NO_SELF_LOCKING_PARAM);
            return paramValue == NO_SELF_LOCKING_PARAM_YES;
        }
    }

References ProGe::ICDecoderGeneratorPlugin::hasParameterSet(), NO_SELF_LOCKING_PARAM, NO_SELF_LOCKING_PARAM_YES, and ProGe::ICDecoderGeneratorPlugin::parameterValue().

Referenced by generate().

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◆ hasSynchronousReset()

bool DefaultICDecoderGenerator::hasSynchronousReset ( ) const

inlineprivate

Definition at line 1694 of file DefaultICDecoderPlugin.cc.

                                {
        return hasParameterSet(SYNC_RESET) &&
               parameterValue(SYNC_RESET) == ENABLE_FEATURE;
    }

References ENABLE_FEATURE, ProGe::ICDecoderGeneratorPlugin::hasParameterSet(), ProGe::ICDecoderGeneratorPlugin::parameterValue(), and SYNC_RESET.

Referenced by generate(), and readParameters().

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◆ lockTraceStartingCycle()

int DefaultICDecoderGenerator::lockTraceStartingCycle ( ) const

inlineprivate

Returns the starting cycle to be written to the global lock trace given as parameter.

If parameter is not defined use value from busTraceStartingCycle() instead.

Returns: The starting cycle.

Definition at line 1763 of file DefaultICDecoderPlugin.cc.

                                       {
        if (!hasParameterSet(LOCK_TRACE_STARTING_CYCLE)) {
            return busTraceStartingCycle();
        } else {
            string paramValue = parameterValue(LOCK_TRACE_STARTING_CYCLE);
 
            if (paramValue == BUS_TRACE_STARTING_CYCLE) {
               return busTraceStartingCycle();
            }
 
            try {
                unsigned int cycle = Conversion::toUnsignedInt(paramValue);
                return cycle;
            } catch (const Exception&) {
                return 0;
            }
        }
    }

References BUS_TRACE_STARTING_CYCLE, busTraceStartingCycle(), ProGe::ICDecoderGeneratorPlugin::hasParameterSet(), LOCK_TRACE_STARTING_CYCLE, ProGe::ICDecoderGeneratorPlugin::parameterValue(), and Conversion::toUnsignedInt().

Referenced by readParameters().

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◆ readParameters()

void DefaultICDecoderGenerator::readParameters ( )

inlineprivatevirtual

Reads parameters and configures the IC and decoder generators.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1881 of file DefaultICDecoderPlugin.cc.

                     {
        icGenerator_->setExportBustrace(generateDebugger());
        decoderGenerator_->setGenerateDebugger(generateDebugger());
        // IC is combinatorial, no need for reset
        decoderGenerator_->setSyncReset(hasSynchronousReset());
 
        if (generateBusTrace()) {
            icGenerator_->setGenerateBusTrace(true);
            icGenerator_->setBusTraceStartingCycle(busTraceStartingCycle());
        } else {
            icGenerator_->setGenerateBusTrace(false);
            decoderGenerator_->setGenerateBusEnable(false);
        }
 
        if (generateLockTrace()) {
            decoderGenerator_->setGenerateLockTrace(true);
            decoderGenerator_->setLockTraceStartingCycle(
                lockTraceStartingCycle());
        } else {
            decoderGenerator_->setGenerateLockTrace(false);
        }
    }

References busTraceStartingCycle(), decoderGenerator_, generateBusTrace(), generateDebugger(), generateLockTrace(), hasSynchronousReset(), icGenerator_, lockTraceStartingCycle(), DefaultICGenerator::setBusTraceStartingCycle(), DefaultICGenerator::setExportBustrace(), DefaultDecoderGenerator::setGenerateBusEnable(), DefaultICGenerator::setGenerateBusTrace(), DefaultDecoderGenerator::setGenerateDebugger(), DefaultDecoderGenerator::setGenerateLockTrace(), DefaultDecoderGenerator::setLockTraceStartingCycle(), and DefaultDecoderGenerator::setSyncReset().

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◆ requiredRFLatencies()

virtual std::set< int > DefaultICDecoderGenerator::requiredRFLatencies ( const TTAMachine::ImmediateUnit & iu ) const

inlinevirtual

Returns the required latency of the hardware implementation of the given immediate unit.

Parameters

iu	The immediate unit.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1604 of file DefaultICDecoderPlugin.cc.

                                                                 {
        return decoderGenerator_->requiredRFLatencies(iu);
    }

References decoderGenerator_, and DefaultDecoderGenerator::requiredRFLatencies().

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◆ verifyCompatibility()

virtual void DefaultICDecoderGenerator::verifyCompatibility ( ) const

inlinevirtual

Verifies that the plugin is compatible with the machine.

Exceptions

InvalidData If the plugin is not compatible with the machine.

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1615 of file DefaultICDecoderPlugin.cc.

                                {
        int requiredDelaySlots = calculateSupportedDelaySlots();
        int specifiedDelaySlots = ttamachine_.controlUnit()->delaySlots();
 
        if (specifiedDelaySlots != requiredDelaySlots) {
            throw InvalidData(
                __FILE__, __LINE__, __func__,
                TCEString("Decoder generator supports ") +
                    Conversion::toString(requiredDelaySlots + 1) +
                    "-stage transport pipeline of GCU with given options. "
                    "Given machine has " +
                    Conversion::toString(specifiedDelaySlots + 1) +
                    " stages");
        }
 
        icGenerator_->verifyCompatibility();
        decoderGenerator_->verifyCompatibility();
    }

References __func__, calculateSupportedDelaySlots(), TTAMachine::Machine::controlUnit(), decoderGenerator_, TTAMachine::ControlUnit::delaySlots(), icGenerator_, Conversion::toString(), ttamachine_, DefaultDecoderGenerator::verifyCompatibility(), and DefaultICGenerator::verifyCompatibility().

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◆ vhdlDirection()

static std::string DefaultICDecoderGenerator::vhdlDirection ( ProGe::Direction direction )

inlinestaticprivate

Converts the given direction to a string.

Parameters

direction The direction.

Returns: The direction as string in VHDL.

Definition at line 1799 of file DefaultICDecoderPlugin.cc.

                                            {
        switch (direction) {
            case ProGe::IN:
                return "in";
            case ProGe::OUT:
                return "out";
            case ProGe::BIDIR:
                return "inout";
        }
        assert(false);
        return std::string();
    }

References assert, ProGe::BIDIR, ProGe::IN, and ProGe::OUT.

◆ writeGlobalDefinitions()

virtual void DefaultICDecoderGenerator::writeGlobalDefinitions	(	HDL	language,
		std::ostream &	pkgStream
	)		const

inlineprivatevirtual

Returns global package definitions in the form of a stream specifically for the variable length instruction architecture.

Parameters

pkgStream The destination stream

Implements ProGe::ICDecoderGeneratorPlugin.

Definition at line 1642 of file DefaultICDecoderPlugin.cc.

                                                                      {
        if (language == ProGe::VHDL) {
            pkgStream << "  -- instruction width" << endl
                      << "  constant INSTRUCTIONWIDTH : positive := "
                      << bem().width() << ";" << endl;
        } else if (language == ProGe::Verilog) {
            pkgStream << "// instruction width" << endl
                      << "parameter INSTRUCTIONWIDTH = " << bem().width()
                      << endl;
        }
    }